CN113884852A - I2C link signal testing method and circuit - Google Patents
I2C link signal testing method and circuit Download PDFInfo
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- CN113884852A CN113884852A CN202111000703.0A CN202111000703A CN113884852A CN 113884852 A CN113884852 A CN 113884852A CN 202111000703 A CN202111000703 A CN 202111000703A CN 113884852 A CN113884852 A CN 113884852A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
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Abstract
The invention provides a test method and a circuit of an I2C link signal, wherein the test method comprises the steps of carrying out analog-to-digital conversion on the link signal, comparing the converted signal by a processor, and detecting the maximum value of the link signal; and the link signal is accessed into a voltage comparator, and the processor detects the rising time and the falling time of the link signal according to the output of the voltage comparator. According to the invention, the I2C link signal is respectively connected with the analog-to-digital converter and the comparator, the processed signal is sent to the processor, the processor analyzes the processed signal to obtain the test result of the I2C link signal, the whole process does not need manual operation, and the board card test efficiency can be greatly improved. When the integrated circuit board was designed, branch of academic or vocational study is direct with this scheme design on-board, for later stage test provides lasting facility, and can be used for the fault detection of integrated circuit board use simultaneously.
Description
Technical Field
The invention relates to the technical field of circuit signal testing, in particular to a method and a circuit for testing an I2C link signal.
Background
An I2C (Inter-Integrated Circuit, a bi-directional synchronous serial bus) bus is a very common way of communication between chips. In order to ensure the reliability of the link signal quality, hardware engineers need to test the reliability of the link signal.
The existing testing method uses an oscilloscope, a hardware engineer accesses an I2C link signal into the oscilloscope, and tests the I2C link signal parameters by observing and recording the waveform change of the oscilloscope, the work is very complicated, and in the process of grabbing the waveform by the oscilloscope, short circuit is caused by improper operation, and the board card is damaged.
Disclosure of Invention
The invention provides a method and a circuit for testing an I2C link signal, which are used for solving the problem of complex existing testing means.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a method for testing an I2C link signal, which comprises the following steps:
performing analog-to-digital conversion on the link signals, comparing the converted signals by a processor, and detecting the most value of the link signals;
and the link signal is accessed into a voltage comparator, and the processor detects the rising time and the falling time of the link signal according to the output of the voltage comparator.
Further, the analog-to-digital conversion is performed on the link signal, the processor compares the converted signal, and the most value of the detected link signal is specifically:
respectively connecting a clock signal and a data signal with an analog-to-digital converter, wherein the analog-to-digital converter respectively acquires voltage values of the clock signal and the data signal in a link transmission process;
and the processor acquires and compares the voltage values to respectively obtain the most value of the clock signal and the most value of the digital signal in the transmission process.
Further, accessing the link signal to a voltage comparator specifically includes:
the clock signal is respectively connected into a first comparator and a third comparator, the reference voltage of the first comparator is a first voltage, and the reference voltage of the third comparator is a second voltage;
and respectively connecting the data signals into a second comparator and a fourth comparator, wherein the reference voltage of the second comparator is a first voltage, and the reference voltage of the fourth comparator is a second voltage.
Further, the detecting, by the processor, the rise time and the fall time of the link signal according to the output of the voltage comparator specifically includes:
the time difference of the output high level of two comparators connected with the same link is the rising time of the current link signal, and the time difference of the output high level is the time difference of the output first high level of one comparator after the other comparator outputs the high level;
the time difference of the output low level of the two comparators connected with the same link is the falling time of the current link signal, and the time difference of the output low level is the time difference of the output first low level of one comparator after the other comparator outputs the low level.
Further, the method includes the processor detecting a high level time and a low level time of the link signal according to an output of the voltage comparator.
Further, the detecting, by the processor, the high level time and the low level time of the link signal according to the output of the voltage comparator specifically includes:
the first comparator continuously outputs low level time which is the low level time of the clock signal, and the first voltage is 0.3 Vcc;
the third comparator continuously outputs high level time which is the high level time of the clock signal, and the second voltage is 0.7 Vcc;
the time for which the second comparator continuously outputs the low level is the low level time of the data signal;
the fourth comparator continues to output the high level for a period of time corresponding to the high level of the data signal.
Further, the method further comprises the step that the processor detects the establishment time and the holding time of the link signal according to the output of the voltage comparator.
Further, the processor detects the setup time and the hold time of the link signal according to the output of the voltage comparator specifically as follows:
the time from the third comparator outputting a high level to the fourth comparator outputting a first low level is the initial signal establishing time;
the time from the second comparator outputting the low level to the third comparator outputting the first high level is the holding time of the initial signal;
the time from the output of the third comparator to the output of the first high level of the second comparator is the stop signal holding time;
the fourth comparator outputs high level, and the time from the first comparator outputting the first high level is used for establishing time for the data signal; or the time from the output of the low level by the second comparator to the output of the first high level by the first comparator establishes time for the data signal;
the time from the first comparator outputting a low level to the second comparator outputting a first high level is the data signal holding time; or the time from the first comparator outputting the low level to the fourth comparator outputting the first low level is the data signal holding time.
The invention provides a test circuit of an I2C link signal, which comprises an I2C link signal, an analog-to-digital converter, a voltage comparator and a processor;
the analog-to-digital converter is respectively connected with the I2C link signal and the processor, and the processor compares the signals converted by the analog-to-digital converter and detects the maximum value of the link signal;
the voltage comparator is respectively connected with the I2C link and the processor, and the processor detects the rising time and the falling time of a link signal according to the output of the voltage comparator.
Further, the comparator comprises a first comparator, a second comparator, a third comparator and a fourth comparator; the reference voltages of the first comparator and the second comparator are both first voltages, the reference voltages of the third comparator and the fourth comparator are both second voltages, the first comparator and the third comparator are connected with clock signals, and the second comparator and the fourth comparator are connected with data signals.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
according to the invention, the I2C link signal is respectively connected with the analog-to-digital converter and the comparator, the processed signal is sent to the processor, the processor analyzes the processed signal to obtain the test result of the I2C link signal, the whole process does not need manual operation, and the board card test efficiency can be greatly improved. When the integrated circuit board was designed, branch of academic or vocational study is direct with this scheme design on-board, for later stage test provides lasting facility, and can be used for the fault detection of integrated circuit board use simultaneously.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of the test method of the present invention;
FIG. 2 is a schematic diagram of the test circuit of the present invention;
fig. 3 is a timing diagram of the I2C link of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
As shown in fig. 1, the method for testing I2C link signals provided by the present invention includes the following steps:
s1, performing analog-to-digital conversion on the link signal, comparing the converted signal by the processor, and detecting the most value of the link signal;
and S2, connecting the link signal into the voltage comparator, and detecting the rising time and the falling time of the link signal by the processor according to the output of the voltage comparator.
The I2C link signal includes a clock signal SCL and a data signal SDA.
The above method is implemented based on a test circuit, which comprises a clock signal SCL, a data signal SDA, an analog-to-digital converter, a voltage comparator and a processor, as shown in fig. 2. The analog-to-digital converter comprises an analog-to-digital converter 1 and an analog-to-digital converter 2 for acquiring a clock signal and a data signal, respectively. The analog-to-digital converter is respectively connected with the I2C link signal and the processor, and the processor compares the signals converted by the analog-to-digital converter and detects the maximum value of the link signal; the voltage comparator is respectively connected with the I2C link and the processor, and the processor detects the rising time and the falling time of the link signal according to the output of the voltage comparator.
The voltage comparator comprises a first comparator, a second comparator, a third comparator and a fourth comparator; the reference voltages of the first comparator and the second comparator are both first voltages, the reference voltages of the third comparator and the fourth comparator are both second voltages, the first comparator and the third comparator are connected with clock signals, and the second comparator and the fourth comparator are connected with data signals.
The processor has a General Purpose Input Output (GPIO) function, and can quickly detect a high-low level jump Output by the comparator, such as an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable logic device).
The first voltage is 0.3Vcc, the second voltage is 0.7Vcc, the reference voltage is selected based on the standard protocol of I2C bus, and when the voltage is higher than 0.7Vcc, the processor converts it to digital 1, and when the voltage is lower than 0.3Vcc, the processor converts it to digital 0. Vcc is the voltage of the I2C link, typically 1.8V or 3.3V.
During the test, the I2C host sends specific characters, and according to the I2C protocol, the parameters of the signal quality test include high and low levels, rising and falling time, high and low level time, and signal establishing and holding time. The specific character comprises a start mark, a device address, a read-write mark bit, a read-write data bit number, read-write data and stop bit information.
In step S1, the link signal is analog-to-digital converted, and the processor compares the converted signal, and the most value of the link signal is detected as: the clock signal is connected with the analog-to-digital converter 1, the data signal is connected with the analog-to-digital converter 2, and the analog-to-digital converter converts the voltage analog quantity into digital quantity and sends the digital quantity to the processor. And the processor records the digital quantity and temporarily stores the digital quantity in the built-in flash, and compares the data after sampling to respectively obtain a maximum value VH and a minimum value VL, namely the high and low levels of the link signal.
As shown in fig. 3, in step S2, the step of detecting the rise time and the fall time of the link signal by the processor according to the output of the voltage comparator is specifically as follows:
the time difference of the output high level of the two comparators connected with the same link is the rising time TR of the current link signal, and the time difference of the output high level is the time difference of the output high level of the other comparator after the other comparator outputs the high level. For example, the rising time of the clock signal is determined by the time difference between the first comparator outputting a high level and the third comparator outputting a first high level.
The time difference of the output low level of the two comparators connected with the same link is the falling time TF of the current link signal, and the time difference of the output low level is the time difference of the output first low level of one comparator after the other comparator outputs the low level. For example, the falling time of the clock signal is determined by the time difference between the first comparator outputting the first low level after the third comparator outputting the low level.
The processor detects the high level time and the low level time of the link signal according to the output of the voltage comparator, and specifically comprises the following steps: the first comparator continuously outputs the time of low level, which is the low level time TLOW of the clock signal; the third comparator continuously outputs the time of high level, which is the high level time THIGH of the clock signal; the time for which the second comparator continuously outputs the low level is the low level time of the data signal; the fourth comparator continues to output the high level for a period of time corresponding to the high level of the data signal.
The processor detects the establishment time and the retention time of the link signal according to the output of the voltage comparator, and specifically comprises the following steps: the time between the third comparator outputting a high level and the fourth comparator outputting the first low level is the start signal setup time (TSU; STA); the time from the second comparator outputting a low level to the third comparator outputting the first high level is the start signal hold time (THD; STA); the time between the third comparator outputting a high level and the second comparator outputting the first high level is the stop signal hold time (TSU; STO); the time between the fourth comparator outputting a high level and the first comparator outputting the first high level is the data signal setup time (TSU; DAT); or the time between the output of the low level by the second comparator and the output of the first high level by the first comparator, establishes a time (TSU; DAT) for the data signal; the time between when the first comparator outputs a low level and when the second comparator outputs a first high level is a data signal holding time (THD; DAT); or the time between the first comparator outputting the low level and the fourth comparator outputting the first low level is the data signal holding time (THD; DAT).
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (10)
1. A method for testing an I2C link signal, characterized by comprising the following steps:
performing analog-to-digital conversion on the link signals, comparing the converted signals by a processor, and detecting the most value of the link signals;
and the link signal is accessed into a voltage comparator, and the processor detects the rising time and the falling time of the link signal according to the output of the voltage comparator.
2. The method for testing the I2C link signal according to claim 1, wherein the link signal is analog-to-digital converted, the processor compares the converted signals, and the most value of the link signal is detected as:
respectively connecting a clock signal and a data signal with an analog-to-digital converter, wherein the analog-to-digital converter respectively acquires voltage values of the clock signal and the data signal in a link transmission process;
and the processor acquires and compares the voltage values to respectively obtain the most value of the clock signal and the most value of the digital signal in the transmission process.
3. The method for testing the I2C link signal according to claim 1, wherein the step of switching the link signal into the voltage comparator is specifically as follows:
the clock signal is respectively connected into a first comparator and a third comparator, the reference voltage of the first comparator is a first voltage, and the reference voltage of the third comparator is a second voltage;
and respectively connecting the data signals into a second comparator and a fourth comparator, wherein the reference voltage of the second comparator is a first voltage, and the reference voltage of the fourth comparator is a second voltage.
4. The method for testing the I2C link signal according to claim 3, wherein the processor detects the rise time and the fall time of the link signal according to the output of the voltage comparator specifically comprises:
the time difference of the output high level of two comparators connected with the same link is the rising time of the current link signal, and the time difference of the output high level is the time difference of the output first high level of one comparator after the other comparator outputs the high level;
the time difference of the output low level of the two comparators connected with the same link is the falling time of the current link signal, and the time difference of the output low level is the time difference of the output first low level of one comparator after the other comparator outputs the low level.
5. The method of claim 3 for testing the I2C link signal further comprising the step of the processor detecting the high time and the low time of the link signal based on the output of the voltage comparator.
6. The method for testing the I2C link signal according to claim 5, wherein the processor detects the high level time and the low level time of the link signal according to the output of the voltage comparator, and specifically comprises:
the first comparator continuously outputs low level time which is the low level time of the clock signal, and the first voltage is 0.3 Vcc;
the third comparator continuously outputs high level time which is the high level time of the clock signal, and the second voltage is 0.7 Vcc;
the time for which the second comparator continuously outputs the low level is the low level time of the data signal;
the fourth comparator continues to output the high level for a period of time corresponding to the high level of the data signal.
7. The method of claim 3 for testing the I2C link signal, further comprising the step of the processor detecting the setup time and hold time of the link signal based on the output of the voltage comparator.
8. The method for testing the I2C link signal according to claim 7, wherein the processor detecting the setup time and the hold time of the link signal according to the output of the voltage comparator is specifically:
the time from the third comparator outputting a high level to the fourth comparator outputting a first low level is the initial signal establishing time;
the time from the second comparator outputting the low level to the third comparator outputting the first high level is the holding time of the initial signal;
the time from the output of the third comparator to the output of the first high level of the second comparator is the stop signal holding time;
the fourth comparator outputs high level, and the time from the first comparator outputting the first high level is used for establishing time for the data signal; or the time from the output of the low level by the second comparator to the output of the first high level by the first comparator establishes time for the data signal;
the time from the first comparator outputting a low level to the second comparator outputting a first high level is the data signal holding time; or the time from the first comparator outputting the low level to the fourth comparator outputting the first low level is the data signal holding time.
9. The test circuit of the I2C link signal comprises an I2C link signal, and is characterized by further comprising an analog-to-digital converter, a voltage comparator and a processor;
the analog-to-digital converter is respectively connected with the I2C link signal and the processor, and the processor compares the signals converted by the analog-to-digital converter and detects the maximum value of the link signal;
the voltage comparator is respectively connected with the I2C link and the processor, and the processor detects the rising time and the falling time of a link signal according to the output of the voltage comparator.
10. The circuit for testing an I2C link signal of claim 9, wherein the comparator includes a first comparator, a second comparator, a third comparator and a fourth comparator; the reference voltages of the first comparator and the second comparator are both first voltages, the reference voltages of the third comparator and the fourth comparator are both second voltages, the first comparator and the third comparator are connected with clock signals, and the second comparator and the fourth comparator are connected with data signals.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4968902A (en) * | 1989-08-02 | 1990-11-06 | Tektronix, Inc. | Unstable data recognition circuit for dual threshold synchronous data |
| JP2007101293A (en) * | 2005-10-03 | 2007-04-19 | Advantest Corp | Signal measuring apparatus |
| CN101636991A (en) * | 2007-02-27 | 2010-01-27 | 佳能株式会社 | Data communications equipment, data communication system and data communications method |
| US20150035509A1 (en) * | 2013-07-31 | 2015-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Control circuit and dc-dc converter |
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- 2021-08-27 CN CN202111000703.0A patent/CN113884852B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4968902A (en) * | 1989-08-02 | 1990-11-06 | Tektronix, Inc. | Unstable data recognition circuit for dual threshold synchronous data |
| JP2007101293A (en) * | 2005-10-03 | 2007-04-19 | Advantest Corp | Signal measuring apparatus |
| CN101636991A (en) * | 2007-02-27 | 2010-01-27 | 佳能株式会社 | Data communications equipment, data communication system and data communications method |
| US20150035509A1 (en) * | 2013-07-31 | 2015-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Control circuit and dc-dc converter |
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