JPH02151773A - Logic analyzer - Google Patents

Abstract

PURPOSE:To accurately and easily enable data observation at the time of repetitive measurement and stop operation of the repetitive measurement in a specific state by providing an interval of time between the end of each measurement and the start of the next measurement at the time of repetitive measurement. CONSTITUTION:A delay counter 11 starts to operate with a trigger detection signal and stops when a prespecified number of delays have been counted. When the counter 11 stops, a memory address counter 12 also stops simultaneously, and memory operation of sampled/latched 13 signals to a buffer memory is completed. Then, all of the stored 13 signals are transferred to an acquisition memory 14. Data of this memory 14 is transferred to a video RAM 15. A display control circuit 16 reads the contents of the RAM 15 and generates video signals and horizontal and vertical synchronous signals to be displayed 17. Control of this series of operation is performed by a CPU 18 according to a program stored in the RAM 15 while information from a keyboard 20 and logic state of hardware are monitored.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is directed to a logic analyzer used in an oscilloscope, etc., which has the function of repeatedly performing the series of operations from sampling an input digital signal to displaying it on a display device. Regarding.

BACKGROUND OF THE INVENTION Conventional logic analyzers perform single measurements, in which a series of operations dedicated to sampling an input digital signal, detecting a trigger event, storing the sampled data, and displaying the stored data are performed only once; It is configured to perform repeated measurements (hereinafter referred to as repeat measurements) in which a series of operations are repeated. Therefore, during repeat measurements, there is no need to perform a measurement start operation for each measurement, and the measurement data is updated and displayed on the display device after each measurement, so you can make optimal measurements while observing changes in the state of the input digital signal. Conditions and measurement data display conditions can be specified.

Furthermore, the system is designed to shorten the time from the end of a measurement to the start of the next measurement by increasing the speed of the display circuit and making the data processing algorithm more efficient. can be done.

Problems to be Solved by the Invention However, in the conventional logic analyzer described above, during repeat measurement, the next measurement starts immediately after the data is displayed after the measurement is completed. There is a problem in that it is difficult to visually observe the state of the signals 11 and identify differences between the signals 11. In addition, if you want to stop the measurement when the measurement data reaches a certain state while observing the measurement data each time and analyze the measurement data in detail, you can recognize the measurement data and repeat measurement stop 1-operation. Since the repeat measurement interval is faster than the time it takes to perform the measurement, there is a problem in that it is not possible to reliably stop the repeat measurement after the corresponding measurement is completed.

The present invention solves these conventional problems by providing a logic analyzer with a function to set and change the time from when data is displayed after measurement to when the next measurement starts during repeat measurements. The purpose is to provide.

Means for Solving the Problems In order to achieve the above-mentioned objects, the present invention provides sampling of input digital signals (5) and detection of trigger (11) events.

a measuring means for repeatedly performing a series of measurements such as storing sampled data and displaying stored data;
It is equipped with a step for setting the time from the measurement line r to the start of the next measurement during memorization and repeat measurement, and a means for counting the L setting time, and a means for setting or changing the repeat measurement interval time in the repeat measurement. This is a logic analyzer that can observe display data and stop repeated measurements when a specific display state is reached.

According to the present invention, during repeat measurements, the time (
By setting C), it is possible to change the measurement interval while executing repeat full + constant, and it is possible to operate at the optimal measurement interval while observing the measurement data of each time on the data display screen 1, =. Therefore, operations can be performed accurately to identify the displayed data and to stop repeat measurement in a certain specific state.

Furthermore, 11? By setting the i-time period (shi) to O, it is possible to improve measurement efficiency during repeat measurements and speed up the display data update cycle, which conventional logic analyzers have.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. The 13-inch digital signal input to the probe 1 is converted by the comparator in the probe 1 to the threshold voltage sent from the [)/Δ converter 2. The signals are compared, logically shaped into high and low levels, and sent to the sample/latch circuit 3. The clock selection circuit 4 selects whether to use the external clock sent from the probe 5 or the internal clock generated by the clock generator 6 as the sampling clock. The signal sent to the sample/latch circuit 3 is sampled by the sampling clock from the clock selection circuit 4. A glitch detection circuit 7 detects a glitch between sampling clocks and sends a detection signal to a detection circuit 8. The word detection circuit 9 compares the preset word with the signal sampled by the sample/latch circuit 3, and detects when they match (sends +i to the trigger detection circuit 8. Edge detection circuit I
O was sampled by sample/latch circuit 3 (At;
☆] The rising or falling edge is detected and the bird sends a detection signal to the detection circuit 8. The trigger detection circuit 8 synthesizes the detection signals from the sample/latch circuit 3, the word detection circuit 9, and the edge detection circuit 10 using a preset combination, and sends the trigger detection slope 5'F to the delay counter 11. The delay counter 11 starts operating in response to a trigger detection signal, and stops after counting a preset number of delays. Delay counter 11 stops
When the signal goes low, the memory address counter 12 also stops at the same time, and the storage operation of the signal sampled by the sample/latch circuit 3 into the buffer memory 13 ends. ] When the recording operation is completed, all signals stored in the buffer memory 13 are transferred to the acquisition memory 14. The data in the acquisition memory 14 is displayed in one display format (
Processing is performed according to the slide display, timing display, and graph display screen, and the video is transferred to video I<AMI5. Display control circuit 16 always uses video RAM+
5 and generates a vertical synchronization signal for display on the display device 17.

] The control of the second series of motions is as follows: Cl5L month 8 is lseOM
This is done by monitoring the information from the keyboard 20 and the logical state of the hardware according to a single stored program.

A reference memory 21 temporarily stores the contents of the acquisition memory 14 by transferring them thereto. 2
Reference numeral 2 denotes a work RAM that is required when the CI)tJ18 performs a series of processes.

At the time of repeat measurement, the series of operations in +iii are repeated.

FIG. 2 is a timing display screen according to this embodiment, and FIG. 3 is a block diagram of a counting section for the time (+,). When there is a key input from the keyboard 20 to execute repeat measurement, it is displayed in the repeat measurement setting field 23, and CI)U
I8 sets the time (1111) and displays the beat measurement interval setting field 24 in accordance with the program 11 of 110M+9. 25 is timing display data.

The time set in field 24 by key entry is C
It is read by the PLJ 18 and set in the timer 29.

In the second diagram, 26 is a time setting signal for CPU 1.
8 sends a display end signal 27 to the timer 29 when the measurement is completed and the display of the measured data is completed. Timer 29 is C
Upon receiving the display end signal 27 from the PLJ 113, it starts counting. When the timer 29 finishes counting for a preset time, (1) it indicates the end of counting to U18 and indicates -28.
send. CP tJ I[l receives the count line r signal 28 from the timer 29 and outputs a command to start the next measurement.

As described above, according to the embodiment L, the repeat measurement interval can be changed by setting the time in the repeat measurement interval setting field 24 using the keyboard 20, so that the recognition display data of display data during repeat measurement can be changed. Repeat measurement stop 1-operation when a certain condition occurs can be performed accurately and easily.

In addition, in the above embodiment, the time (shi) is expressed as a numerical value and (11
However, as shown in Fig. 4, it may be set as a relative time, and the length of the bar display 30 is -1, 2.
Corresponds to time (1,).

Effects of the Invention Since the present invention has the above-described configuration, a time is provided between each measurement path r and the start of the next measurement during repeat measurements, and data observation during repeat measurements and repeat measurements in specific conditions are possible. The stop + and l- operations can be performed accurately and easily. Further, since the above-mentioned time setting can be changed while performing data observation by repeat measurement, the effect that the time can be set to the optimum time according to the observed state is achieved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a logic analyzer showing an embodiment of the present invention, Fig. 2 is a timing display diagram of the same logic analyzer, Fig. 3 is a block diagram of the time counter, and Fig. 4 is a block diagram of another logic analyzer using the same logic analyzer. It is a timing display diagram. 23... Repeat measurement setting field 24... Repeat measurement interval setting field 25... Timing display data

Claims (1)

[Claims] (1) A measuring means that repeatedly performs a series of measurements such as sampling an input digital signal, detecting a trigger event, storing sampled data, and displaying the stored data, and a measuring means that repeatedly performs a series of measurements such as sampling an input digital signal, detecting a trigger event, storing the sampled data, and displaying the stored data. The method includes a means for setting a time until the start of the next measurement and a means for counting the set time, and the display data is observed by setting or changing the repeat measurement interval time in repeated measurements.
A logic analyzer characterized in that repeated measurements are stopped when a specific display state is reached.