SU991453A1

SU991453A1 - Signal shape recognition device

Info

Publication number: SU991453A1
Application number: SU813340077A
Authority: SU
Inventors: Владимир Константинович Миртов; Владимир Николаевич Лясин
Original assignee: Рижское Высшее Военно-Политическое Краснознаменное Училище Им.Маршала Советского Союза Бирюзова С.С.
Priority date: 1981-09-22
Filing date: 1981-09-22
Publication date: 1983-01-23

Description

Изобретение относится к автоматике и вычислительной технике, а именно к классу устройств для распознавания образов. 5The invention relates to automation and computing, and in particular to a class of devices for pattern recognition. 5

Известны устройства для распозна- . вания формы сигналов, использующие спектральное разложение сигнала и сравнении его спектра с эталонным.Known devices for recognition. waveforms using the spectral decomposition of the signal and comparing its spectrum with the reference one.

Известно устройство, содержащее щ блок ввода сигналов, соединенный с первым и вторым генераторами импульсов, с блоком ввода сигналов и с синхронизатором, соединенным с формирователем импульсов и с пороговым элементом, соединенным с сумматором, вхо- ’* ды которого подключены к логическому блоку [1].A device is known comprising a signal input unit connected to the first and second pulse generators, with a signal input unit and with a synchronizer connected to a pulse former and with a threshold element connected to an adder, the inputs of which are connected to a logic unit [1 ].

Недостаток этого устройства состоит в невысокой надежности распозна- 2Q вания объектов.The disadvantage of this device is the low reliability of 2Q recognition of objects.

Наиболее близким к предлагаемому является устройство, содержащее блок ввода, анализатор спектра Фурье-Хаара, делитель напряжения, сумматор, пороговый элемент, блок управления, блок хранения эталонов, блок записи эталонов и формирователь импульсов С 2].Closest to the proposed one is a device containing an input unit, a Fourier-Haar spectrum analyzer, a voltage divider, an adder, a threshold element, a control unit, a standard storage unit, a standard recording unit, and a pulse shaper C 2].

Недостаток устройства состоит в недостаточно высокой надежности распознавания. •’θThe disadvantage of this device is the lack of recognition reliability. • ’θ

Цель изобретения - повышение надежности устройства.The purpose of the invention is to increase the reliability of the device.

Поставленная цель достигается тем, что в устройство, содержащее блок ввода сигналов, соединенный с первым и вторым генераторами импульсов и с одними входами усилителей, другие входы которых подключены к выходам ключей первой группы, а выходы усилителей соединены с входами соответствующих интеграторов, делитель частоты, подключенный к первому генератору импульсов, к синхрогенератору и к блоку совпадения, выходы которого'соединены с входами ключей первой группы, блок записи эталонов, подключенный к коммутатору, к синхронизатору и к блоку памяти, другой вход которого соединен с синхронизатором, а выходы подключены к формирователю импульсов, пороговый, элемент, соединенный с сумматором и синхронизатором; блоки вычитания, входы которых подключены к соответствующим интеграторам, а выходы соединены с коммутатором, и первый делитель напряжения, подключенный к одному блоку вычитания, к формирователю импульсов и к сумматору, введен блок формирования последовательности сигналов приэна кон, входы которого соединены с вторым генератором импульсов, с блоками вычитания, с синхронизатором и с формирователем импульсов, а выходы подключены к входам сумматора.This goal is achieved by the fact that in a device containing a signal input unit connected to the first and second pulse generators and with one input of the amplifiers, the other inputs of which are connected to the outputs of the keys of the first group, and the outputs of the amplifiers are connected to the inputs of the respective integrators, a frequency divider connected to the first pulse generator, to the sync generator and to the coincidence unit, the outputs of which are connected to the inputs of the keys of the first group, the unit for recording standards connected to the switch, to the synchronizer and to the unit memory, the other input of which is connected to the synchronizer, and the outputs are connected to the pulse shaper, a threshold, an element connected to the adder and synchronizer; subtraction units, the inputs of which are connected to the corresponding integrators, and the outputs are connected to the switch, and the first voltage divider connected to one subtraction unit, to the pulse shaper and to the adder, a block for generating a sequence of signals of the input switch is introduced, the inputs of which are connected to the second pulse generator, with subtraction blocks, with a synchronizer and with a pulse shaper, and the outputs are connected to the inputs of the adder.

При этом блок формирования последовательности сигналов признаков содержит последовательно соединенные счетчик, входы которого являются одними входами блока, дешифратор, ключи второй группы, входы которых являются другими входами блока, и делители напряжения группы, входы которых являются третьими входами блока, а выходы являются выходами блока или группу делителей напряжения, входы которых являются одними входами блока и последовательно соединенные счетчик, входы которого являются другими входами блока, дешифратор и ключи второй группы, одни входы которых подключены к соответствующим делителям напряжения группы, а выходы являются выходами блока.In this case, the block for generating a sequence of signs of signals contains a series-connected counter, the inputs of which are one of the inputs of the block, a decoder, the keys of the second group, the inputs of which are other inputs of the block, and voltage dividers of the group whose inputs are the third inputs of the block, and the outputs are the outputs of a group of voltage dividers, the inputs of which are one of the inputs of the unit and series-connected counter, the inputs of which are other inputs of the unit, the decoder and the keys of the second load PPP, one of the inputs of which are connected to the respective voltage dividers of the group, and the outputs are the outputs of the unit.

На чертеже представлена блок-схема устройства.The drawing shows a block diagram of a device.

Она включает блок 1 ввода сигналов, анализатор 2 спектра, содержащий первый генератор 3 импульсов, делитель 4 частоты, блок 5 совпадения ключи 6 первой группы, усилители 7, интеграторы 8 и блоки 9 вычитания, второй генератор 10 импульсов, блок 11 формирования последовательности сигналов признаков, содержащий счетчик 12, дешифратор 13, ключи 14 второй группы., группу делителей 15 напряжения, включающих цифровое управляемые сопротивления 16, клйочи 17 третьей группы и инверторы 18, сумматор 19, пороговый элемент 20, синхронизатор 21, блок 22 памяти, блок 23 записи эталонов, формирователь 24 импульсов, коммутатоо 25 и пер- ⁴вый ___ делитель 26 напряжения,вклю-.It includes a signal input unit 1, a spectrum analyzer 2, comprising a first pulse generator 3, a frequency divider 4, a coincidence block 5, keys 6 of the first group, amplifiers 7, integrators 8 and subtraction blocks 9, a second pulse generator 10, and a feature signal generation block 11 comprising a counter 12, a decoder 13, keys 14 of the second group., a group of voltage dividers 15, including digitally controlled resistance 16, keys 17 of the third group and inverters 18, adder 19, threshold element 20, synchronizer 21, memory block 22, recording unit 23 standards, shaper 24 pulses, commutator 25 and the first ⁴ ___ voltage divider 26, including.

'чающий цифровое управляемое сопротивление 27, ключ 28 и инвертор 29.Digital control resistance 27, key 28 and inverter 29.

Устройство работает следующим образом.The device operates as follows.

Блок 1 преобразует информацию об объекте (графический символ, звуковой сигнал и др.) в электрический сигнал, форму которого необходимо распознать. Для этого он по переднему фронту сигнала формирует и выдает команду, запускающую генераторы 3 и 10 и разрешающую непрерывную их работу до момента окончания входного сигнала, по которому прекращается выдача этой команды. Одновременно с . этим полученный сигнал поступает на анализатор 2, с помощью которого производится разложение сигнала в соответствующий ортогональный ряд·.Block 1 converts information about the object (graphic symbol, sound signal, etc.) into an electrical signal, the shape of which must be recognized. To do this, it generates and issues a command on the leading edge of the signal that starts the generators 3 and 10 and allows their continuous operation until the end of the input signal, by which the issuance of this command stops. At the same time with . this, the received signal is fed to the analyzer 2, with the help of which the signal is expanded into the corresponding orthogonal row ·.

Импульсы с генератора 3 поступают на делитель 4, который формирует на своих выходах сетку частот. Блок 5 выделяет с разных плеч каждого из триггеров делителя 4 два импульса и подает их на ключи 6. Ключи открывают на это время усилители 7, коэффициенты усиления которых пропорциональны амплитуде этих функций, и пропускают сигнал на интеграторы 8, а затем на соответствующий блок 9.The pulses from the generator 3 are fed to a divider 4, which forms a frequency grid at its outputs. Block 5 selects two pulses from different shoulders of each of the triggers of the divider 4 and feeds them to the keys 6. The keys open the amplifiers 7 at this time, the amplification coefficients of which are proportional to the amplitude of these functions, and pass the signal to the integrators 8, and then to the corresponding block 9.

К моменту окончания входного сигнала получаются все коэффициенты, начинаем работу синхронизатор 21, .. который формирует считывающий импульс, поступающий на ячейки блока 22, по которому производится коммутация ключей цифровых управляемых сопротивлений 16 и 27, величина каждого из которых устанавливается пропорциональной соответствующему коэффициенту. Так как коэффициенты разложения эталонных сигналов могут иметь разные знаки, то производится дополнительное переключение, соответствующих аналоговых входов/делителей 15 и 26 с помощью ключей 17 и 28 с инверторами 18 и 29.By the time the input signal ends, all the coefficients are obtained, the synchronizer 21, .., starts working, which generates a read pulse arriving at the cells of block 22, through which the keys of the digital controlled resistances 16 and 27 are switched, the value of each of which is set proportional to the corresponding coefficient. Since the decomposition coefficients of the reference signals can have different signs, an additional switching is performed of the corresponding analog inputs / dividers 15 and 26 using the keys 17 and 28 with inverters 18 and 29.

Продолжительность работы генератора 10 определяется длительностью формируемого блоком 1 сигнала и измеряется количеством импульсов, поступающих на вход счетчика 12 импульсов, устанавливаемого синхронизатором 21 после каждого цикла распознавания в исходное состояние и формирующего на своих выходах комбинацию сигналов, соответствующую количеству поступивших на счетчик импульсов.The duration of the generator 10 is determined by the duration of the signal generated by block 1 and is measured by the number of pulses arriving at the input of the pulse counter 12, which is set by the synchronizer 21 after each recognition cycle to its initial state and generating a combination of signals at its outputs that corresponds to the number of pulses received at the counter.

Дешифратор 13 по достижении счетчиком 12 определенного состояния, которое зависит от реального случая распознавания и определяется для данного случая опытным путем, выдает с 1-го выхода управляющий сигнал на соответствующий ключ 14, разрешая этим прохождение аналогового сигнала с (К+1 )-го выхода анализатора 2 через этот ключ на соответствующие делители 15 и 26. Далее, по мере изменения состояния счетчика 12, дешифратор 13 формирует разрешающие сигналы последовательно на выходах 2,3 и т.д., что доводит оптимальное количество информационных признаков, по которым производится распознавание, до К+2, К+3 и т.д. соответственно.The decoder 13 when the counter 12 reaches a certain state, which depends on the real case of recognition and is determined empirically for this case, issues a control signal from the 1st output to the corresponding key 14, thereby allowing the analog signal to pass from the (K + 1) -th output analyzer 2 through this key to the respective dividers 15 and 26. Further, as the state of the counter 12 changes, the decoder 13 generates enable signals sequentially at outputs 2,3, etc., which brings the optimal number of information signs c, by which recognition is performed, up to K + 2, K + 3, etc. respectively.

При другом варианте конструктивного выполнения блока 11 (на чертеже не показан), выходные сигналы с блоков 9 вычитания поступают на входы соответствующих делителей 15 непосредственно, а напряжения с выходов делителей 15 через ключи второй группы, коммутируемые дешифратором 13, подаются на входы сумматора 19.In another embodiment of the constructive execution of block 11 (not shown in the drawing), the output signals from the subtraction blocks 9 directly go to the inputs of the respective dividers 15, and the voltage from the outputs of the dividers 15 through the keys of the second group, switched by the decoder 13, is fed to the inputs of the adder 19.

В конечном итоге количество информационных признаков, определяемое количеством поступающих сигналов на входа сумматора 19, будет соответствовать оптимальному числу для данной длины входного сигнала и данного случая распознавания.Ultimately, the number of information signs, determined by the number of incoming signals at the input of the adder 19, will correspond to the optimal number for a given length of the input signal and this recognition case.

После окончания переходных процессов на выходе сумматора 19 формируется напряжение, пропорциональное взаимной корреляции входного сигнала и первого эталонного. Если пороговый уровень будет превышен, то пороговый элемент 20 вырабатывает сигнал, поступающий в синхронизатор 21, который может быть использован как сигнал об окончании процесса распознавания.After the end of transients, the output of the adder 19 generates a voltage proportional to the cross-correlation of the input signal and the first reference. If the threshold level is exceeded, the threshold element 20 generates a signal supplied to the synchronizer 21, which can be used as a signal about the end of the recognition process.

Введение нового блока позволило существенно повысить надежность устройства.The introduction of a new unit has significantly improved the reliability of the device.

Claims

The invention relates to automation and computing, namely to a class of pattern recognition devices. Devices are known for recognizing waveforms using spectral decomposition of a signal and comparing its spectrum with a reference one. A device is known that contains a signal input unit connected to the first and second pulse generators, a signal input unit and a synchronizer connected to a pulse shaper and a threshold element connected to an adder, whose inputs are connected to a logic unit with 1. The disadvantage of this The device consists in low reliability of location of objects. The closest to the present invention is a device containing an input unit, a Fourier-Haar spectrum analyzer, a voltage divider, an adder, a threshold element, a control unit, a standard storage unit, a standard recording unit and a C 2 pulse shaper. The disadvantage of the device is insufficient reliability recognition. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that a device containing a signal input unit connected to the first and second pulse generators and one amplifier inputs, the other inputs of which are connected to the outputs of the keys of the first group, and the outputs of the amplifiers are connected to the inputs of the respective integrators, frequency divider connected to the first pulse generator, to the synchronous generator and to the coincidence unit, the outputs of which are connected to the inputs of the keys of the first group, the unit for recording standards, connected to the synchronizer 1, to the synchronizer and to the bl memory, the other input of which is connected to the synchronizer, and the outputs are connected to the driver of the pulses, the threshold, the element connected to the accumulator and the synchronizer, the subtractors, the inputs of which are connected to the corresponding integrator PCI, and the outputs connected to the switch, and the first voltage divider connected to one subtraction unit, to a pulse shaper and to an adder, a block of formation of a sequence of signal signals, the inputs of which are connected to the second pulse generator, with subtraction blocks, with syn a chronizer and a pulse maker, and the outputs are connected to the inputs of the adder. At the same time, the block forming the sequence of indicative signals contains a serially connected counter, the inputs of which are one block inputs, the decoder, the keys of the second group, the inputs of which are other block inputs, and the voltage dividers of the group, the inputs of which are the third block inputs and the outputs are the outputs of the block or a group of voltage dividers whose inputs are the same inputs of the block and the series-connected counter, the inputs of which are the other inputs of the block, the decoder and the keys of the second g uppy, some inputs of which are connected to respective divider m voltage group and outputs are the outputs. The drawing shows a block diagram of the device. It includes a signal input unit 1, a spectrum analyzer 2 containing the first pulse generator 3, a frequency divider 4, block 5 keys of the first group are matched, amplifiers 7, integrators 8 and subtraction blocks 9, the second pulse generator 10, block 11 of forming the sequence of signal signals containing a count 12, a decoder 13, keys 14 of the second group., a group of voltage dividers 15, including digital controllable resistances 16, 17 of the third group and inverters 18, adder 19, threshold element 20, synchronizer 21, block 22 memories, block 23 records this 2, a pulse shaper 2, a switch 25 and a first voltage separator 26 including a digital controlled resistance, 27, a switch 28 and an inverter 29. The device operates as follows. Unit 1 converts information about the object (graphic symbol, sound signal, etc.) into an electrical signal, the shape of which must be recognized. To do this, it forms and issues a command on the leading edge of the signal, which triggers the generators 3 and 10 and allows them to run continuously until the end of the input signal, on which the issuance of this command stops. At the same time, the received signal is fed to analyzer 2, with which the signal is decomposed into the corresponding orthogonal p d-. The pulses from the generator 3 are fed to the divider 4, which forms at its outputs a frequency grid. Block 5 selects two pulses from the different arms of each trigger of divider 4 and feeds them to keys 6. Amplifiers 7 open at this time, the amplification factors of which are proportional to the amplitude of these functions, and pass the signal to integrators 8 and then to the corresponding block 9. By the moment the input signal ends, all coefficients are obtained, we start the synchronizer 21, .. which forms a read pulse arriving at the cells of the block 22, through which the keys of the digital controlled resistances 16 and 27 are switched, the value each of which is set proportional to the corresponding coefficient. Since the coefficients of decomposition of the reference signals may have different signs, additional switching is performed corresponding to analog inputs / dividers 15 and 26 using switches 17 and 28 with inverters 18 and 29. The duration of the generator 10 is determined by the duration of the signal generated by block 1 and measured the number of pulses arriving at the input of the counter 12 pulses set by the synchronizer 21 after each recognition cycle to the initial state and forming at its outputs a combination of signals, with tvetstvuyuschuyu number of pulses received at the counter. The decoder 13, when counter 12 reaches a certain state, which depends on the actual recognition case and is determined for this case empirically, sends a control signal to the corresponding key 14 from the 1st output, allowing the analog signal to pass from (K + 1) output of the analyzer 2 through this key to the corresponding dividers 15 and 26. Further, as the state of the counter 12 changes, the decoder 13 generates resolution signals successively at the outputs 2,3, etc., which brings the optimal amount of informational prizes What are the on which detection is performed until K + 2, K bs, etc. respectively. In another embodiment of the design block 11 (not shown), the output signals from the subtraction blocks 9 are fed to the inputs of the respective dividers 15 directly, and the voltages from the outputs of the dividers 15 through the keys of the second group switched by the decoder 13 are fed to the inputs of the adder 19. Ultimately, the number of information signs, determined by the number of incoming signals to the inputs of the adder 19, will correspond to the optimal number for a given length of the input signal and a given recognition case. After termination of the transient processes, a voltage is formed at the output of the adder 19, which is proportional to the mutual correlation of the input signal and the first reference voltage. If the threshold level is exceeded, then the threshold element 20 generates a signal entering the synchronizer 21, which can be used as a signal that the recognition process has ended. The introduction of a new unit has significantly improved the reliability of the device. Claim 1. A device for recognizing a waveform containing a signal input unit connected to the first and second pulse generators and one input of amplifiers, the other inputs of which are connected to the outputs of the keys of the first group, and the outputs of the amplifiers are connected to the inputs of the respective integrators, frequency divider connected to the first pulse generator, to the synchronous generator and to the coincidence unit, the outputs of which are connected to the inputs of the keys of the first group, the recording unit of the standards, connected to the switch, to the sync the lower unit and the memory unit, the other input of which is connected to the synchronizer, and the outputs are connected to the pulse shaper, the threshold element connected to the adder and the synchronizer subtractors whose inputs are connected to the appropriate integrators. and the outputs are connected to the switch, and the first voltage divider connected to one subtraction unit, to the pulse former and to a slotter, differing in that, in order to improve the reliability of recognition, it contains a signal sequence generator, the inputs of which are connected by a second pulse generator , with subtractors, with a synchronizer with the pulse shaper, and the outputs are connected to the inputs of the adder. 2. The device according to claim 1, DIFFERENT in that the signal generation unit of the signs consists of series-connected counter, the inputs of which are the same inputs of the block, the decoder, the keys of the second group, the inputs of which are other inputs of the block, and divisors The group of inputs whose inputs are the third inputs of the block and the outputs are the outputs of the block .. 3. The device according to claim 1, characterized in that the block for forming the sequence of the signal of attributes contains a group of voltage dividers whose inputs are The unit inputs and serially connected meter whose inputs are other inputs of the unit, the decoder and the keys of the second group, one inputs of which are connected to the corresponding voltage dividers of the group, and the outputs are the outputs of the unit. Sources of information taken into account in the examination 1. US patent number 3936800, cl. 340-146.3, pub. 1976.

2. Authors certificate of the USSR 467374, cl. G 06 K 9/00, 1975 (prototype).,