SU1495724A2 - Pulse edge duration meter - Google Patents

Abstract

The invention relates to a measuring technique and can be used to measure the parameters of pulses in automation, computational and instrumentation technology. The purpose of the invention — extending the functionality of the meter — is achieved as a result of the simultaneous automatic measurement of the durations of the fronts of pulses and their bases and peaks. The meter contains the normalizer 1 pulses, delay elements 2-5, inverters 6-8, peak detectors 9 and 10 with reset, adders 11 and 12, electronic switches 13-16, made in the form of a relay, elements OR 17-19, converters 20- 22 voltage-frequency, counters 23-25, RS-flip-flops 26-28, differentiation units 29 and 30, comparator 31, recorder 32, digital multipliers 33 and 34, digital divider 35, memory unit 36, video amplifier 37. To determine the duration of the top of the pulse under investigation, the difference between the base durations of the pulse under study and the sums is calculated. oh durations of the front and rear fronts. 2 Il.

Description

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The invention relates to measurement technology, can be used to measure the parameters of pulses in an automaton, computer, and instrumentation technology and is an improvement in the device according to the author. No. 1422189.

The aim of the invention is to expand the functionality of the meter due to the simultaneous automatic measurement of the durations of the edges of the pulses and their bases and vertices.

Figure 1 shows the structure of the meter; Fig. 2 illustrates stress plots showing it. the job

The pulse front pulse meter contains a normalizer of 1 pulses, first to fourth delay elements 2-5, first 6, second 7 and third 8 inverters, first 9 and second 10 peak detectors with a reset, first 11 and second 12 tori sum, first to the fourth electronic switches 13-16, made, for example, in the form of high-frequency relays, the first 17, the second 18 and the third 19 OR elements, the first 20, the second 21 and the third 22 voltage frequency converters, the first 23, the second 24 and the third 25 counters, performed, for example, on chips like 133IE5, first 26, 27 and the third 28 RS triggers, the first 29 and the second 30 differentiation units, a comparator 31 made, for example, in the form of an IITt trigger, a recorder 32 made, for example, in the form of a MPU 6-3 digital printer, the first 33 and the second 37 digital multipliers and a digital divider 35, made, for example, on a chip such as 145Sh116, a memory block 36, made, for example, on a chip like K155PE23, and a video amplifier 37..When this normalizer is connected .1 pulses, the output of which is also connected to the input of the first element 2 from the rear and the first input of the comparator 31, the first adder 11, the first inverter 6, the first electronic key 13, the first element OR 17, the second input of which is connected to the normalizer 1 pulse, the second s / tectron key 14, the first peak detector 9, the first converter 20 voltage - frequency, first

o

five

0

5 Oh, 0 s

0

five

the counter 23, the digital divider 35, the first digital multiplier 33, the second information input of which is connected to the output of the memory unit 36, and the recorder 32, connected in series to the second inverter 7, the input of which is connected to the output of the first delay element 2 and the second input of the comparator 31 , the second peak detector 10, the output of which is also connected to the second input of the first adder 11, the second adder 12, the second input of which is connected to the output of the first delay element 2, the third inverter 8, the third electronic switch 15, the second element OR 18, second The second input is connected to the output of the first delay element 2, the second voltage converter 21 is the frequency, the first RS flip-flop 26, the direct output of which is also connected to the control input of the second electronic key 14, the first differentiation unit 29 and the second delay element 3, the first output of which is connected to the control input of the digital divider 35, the third voltage-frequency converter 22 is connected in series, and the second counter 24, the output of which is connected to the second information input of the digital divider 35, sequentially connected to the second differentiation unit 30, the input of which is connected to the output of the comparator 31, the third delay element 4 and the second RS-flip-flop 27, the output of which is connected to the control inputs of the first 13 and third 15 electronic keys, the output of the second delay element 3 is connected to the control switches the first and second peak detectors 9 and 10, the first and second counters 23 and 24, the first digital multiplier 33, the recorder 32, the R-input of the first RS-flip-flop 26 and S-. the second RS flip-flop 28, the S and R inputs of which are connected to the outputs of the first differentiation unit 29 and the third delay element 4, the fourth key 16, the third counter 25, the installation input of which is connected to the output the third delay element 4, and the second digital multiplier 34, the second information and control inputs of which are connected respectively to the second bit outputs of the block

36 and the second output of the second delay element 3, and the output connected to the second information bits of the recorder 32, the fourth delay element 5, the input of which is connected to the output of the first differentiation unit 29, and the third element OR 19, the output of which is connected with informational input of the fourth key 16, the video amplifier 37, the input and output of which are respectively connected to the output of the fourth key 16 and the second input of the third element OR 19.

The device works as follows.

The investigated pulse signal is fed to the input of the normalizer 1 pulses. At its output, amplitude-constant pulses are generated and (FIG. 2a), which are fed to the second input of the comparator 31, the input of the first delay element 2 and the second input of the first element OR 17, from the output of which the first pulse studied is fed to the input of the third converter 22, for example is the frequency that produces counting pulses, the number of which is proportional to the amplitude U of the pulse and counted by the second counter 24, from the output of which their numerical value

in binary code it goes to the first input of the digital divider 35, and through

The second electronic key 14 is supplied to the first peak detector 9 ,. which remembers the change in current PDP voltage (FIG. 26) of the leading edge of the pulse U under study, during time 1 (5 outputs of the first element 2) the delayed pulse (FIG. 2B) goes to the second input of the comparator 3 and through the second element OR 18 to the input of the second voltage converter 21 is the frequency. At the time of forming the beginning of the leading edge of the delayed pulse Uj (Fig.2B, t tj), the output of the first voltage converter 20 is the frequency that the first counting pulse is generated, which is fed to the S input of the first RS flip-flop 26 and translate t it to the position of logical 1 (Fig. 2d). At the direct output of the first RS flip-flop 26, a voltage of logical 1 is formed, which is fed to the input of the first differentiation unit 29 and locks the second electron 95724

key 14, leaving the voltage on the first detector 9 at the level (fig, 26, tt), from the output of the first, peak detector 9, the voltage is fed to the input of the first voltage converter 20 - the frequency that produces counting pulses, the number of which is proportional to 10 voltage and is counted by the first counter 23, from the output of which the value of the counting pulses in the binary code is fed to the first input of the digital divider 35.

15 The leading edge of the pulse U of the first RS flip-flop 26 is differentiated by the first differentiation unit 29, forming a positive pulse Uj. (figd), which is fed to the input

20 of the fourth delay element 5, S is the input of the third RS flip-flop 28, shifting it to the logical 1 position, and after a delay of time C, the second delay element 3 transmits the count results to a digital divider 35, where the ratio of the amplitude Uy of the pulse to the level of change of the leading edge of the pulse and time C (FIG. 2e). Dividing result

30 ui / id-jn is transmitted for the second time delayed "(Fig. 2e) second pulse delay element 3 to the first digital multiplier 33, to which memory unit 36 is supplied

35, the delay value and the recorder 32. At the output of the first digital multiplier 33, the duration is determined from, ,,, and dz / and the leading edge of the pulse being investigated, U, which is recorded by the recorder 32.

The first peak detector 9, the first 23 and second 27 counters, and the first RS flip-flop 26 are returned to

g is the initial state, and the second RS-flip-flop 27 takes on the value of logical 1 (fig. 2zh) and the first and third electronic switches 13 and 14 are opened. At the same time, the output of the third 50 RS flip-flop 28 produces a voltage and, 7 c) which is fed to the control input of the fourth electronic key 16, and delayed by the fourth delay element 5

its pulses are impulse through the third element OR 19 and the open voltage and, 7 the fourth electronic key 16 is fed to the counting input of the third counter 25, which counts

the pulses arriving at its input, and the video amplifier 37. Amplified by an amplifier up to the magnitude of the response of a binary counter, 25 (at least 2.4 V),

the second voltage converter 21 is frequency.

At the time of formation of the beginning of the trailing edge of the delayed pulse

but the U pulse u delayed by Г, U (fig 2n, tt) at the output of the primary cut third element OR 19 again goes through the open fourth electronic key 16 to the counting input of the third counter 25 and the video input 37. At the output video amplifier 37 is again being amplified to counter voltage 25, but delayed pulse Uj ,. which again through the third element 19 through 15 is given through the open fourth electronic key 16 to the counting input of the counter 25, i.e. the formation of a sequence of short high-frequency pulses (Fig. 2m) occurs with a period of –20 following T C during the action of voltage U; at the control input of the electronic key 16,

At the same time, from the output of the first delay element 2, the voltage U, inverted by the second inverter 7, in the form of voltage Ug (Fig. 2h) is fed to the input of the second peak detector 10, which stores the amplitude U of the pulse under study, arriving as voltage U ( Fig. 2i) on a voltage converter 20 — the frequency is again generated by the first counting pulse, which is fed to the S input of the first RS flip-flop 26 and translates it to the logical 1 position (Fig. 2d). At the forward output of the first RS flip-flop 26, a positive voltage is again formed and which is fed to the input of the first differentiation unit 29 and again locks the second electronic key 14, leaving the voltage on the first peak detector 9 at the level of the first 20 and third 22 converters produce counting impulses25

The input of the first adder II, to the first input of which, from the output of the normalizer 1 of the pulses, is applied the voltage and.

., 35

but voltage u, u. and UM, respectively, and counted by the first and second counters 23 and 24, from the outputs of which the counting results in binary code are fed to a digital divider 35o

Again, the first differentiation block 29 differentiates the leading edge of the pulse U4 of the first RS flip-flop 26 (Fig 2g), to which, after a delay of time about the second delay element 3, the counting results of the first 23 and second 24 counters are transmitted to a digital divider 35, where the ratio the amplitude of the pulse Uj to the level of change in voltage of the trailing edge id of the test. The output of the first adder 11 is formed by a negative voltage V d (Fig. 2k), which is inverted by the first inverter 6 (Fig. 2n), as voltage U, through the first electronicspanner 13, the first OR element 17 and the second electronic switch 14 is fed to a first peak detector 9, the output of which is effected the formation of the voltage

and

og

rear

front current

investigated time l

pulse in the input voltage of the first converter 20 is frequency. At the same time, on the first and second inputs of the second adder 12, voltages Vcf- (Fig. 2i) and Of (Fig. 2c) are formed, which at its output form a negative voltage U, (Fig. 2m), which is inverted by a third inverter 8 (fign), through the third electronic key 15 and the second element SHTO 18 is fed to the input

The first voltage converter 20 is the frequency that again produces the first counting pulse, which is fed to the S input of the first RS flip-flop 26 and translates it to the logical 1 position (Fig. 2d). At the forward output of the first RS flip-flop 26, a positive voltage is again formed and which is fed to the input of the first differentiation unit 29 and again locks the second electronic key 14, leaving the voltage on the first peak detector 9 at the level of the first 20 and third 22 converters produce counting impulses 5 0

five

five

but voltage u, u. and UM, respectively, and counted by the first and second counters 23 and 24, from the outputs of which the counting results in binary code are fed to a digital divider 35o

Again, the first differentiation block 29 differentiates the leading edge of the pulse U4 of the first RS flip-flop 26 (Fig 2g), which, after a delay of time about the second delay element 3, the counting results of the first 23 and second 24 counters are transmitted to a digital divider 35, where the ratio the amplitude of the pulse Uj to the level of the change in voltage of the id of the falling front studies a MO pulse in time

At the time of the formation of the back front of the pulse U, as a result of the overvoltage and voltage U, the output of the comparator 31 produces an impedance

(FIG. 2o), the back front of which, differentiated by the second differentiation unit 30 (FIG. 2p), is fed to the R input of the third KZ trigger 28, shifting it to the position of logical O. On the output of the third RS trigger, a voltage is generated living logical

O, the fourth electronic key is closed and counting by pulse counter 25 gg of the pulse sequence U (g is stopped. The result of the division and counting by the counter of the number of pulses is transmitted for the second and second pulse delay element 3 for the first and second digital multipliers 33 and 34, respectively, On which the first and second outputs of the memory block 36 receive values of and, and to the recorder 32 o At the outputs of the first and second digital multipliers 33 and FOR, the values of the lengths of the falling front and Ho p. Ci are based. and the pulse under study and, which are recorded by the recorder 32. At the same time, the pulse delayed by the third delay element 3 (fig-2p) is in the form of a pulse and (fig.2r) is fed to the S input of the second RS trigger 27 and the installation input of the third counter 24, the second RS flip-flop 27 and the third counter 25 return to the initial state and the process of measuring the durations of the fronts and the base of the pulse under study is terminated.

Claims (1)

If necessary, to determine the duration of the tip of the pulse under investigation, the difference Cjji, φ () between the durations of the base of the pulse under study and the sum of the durations of the front and rear edges of the pulse is calculated, and to determine the statistical characteristics of the pulse parameters, the number of measurements is chosen based on the reliability of these measurements. Claims of the invention: Measuring of the duration of pulse fronts by autor.W. W 1422189, about t and h: o y and so that, in order to expand functionality, measure due to the simultaneous automatic measuring pulse rise and duration of their bases and tops, it is further introduced serially connected third RS trigger, the fourth key, the third counter and the second digital multiplier, the fourth delay element and the third element OR, as well as the video amplifier, are connected in series, moreover, the S and R inputs of the third RS trigger are connected respectively to the outputs of the first and second differentiation units, the installation input of the third counter is connected to the output  the third delay element, the second information and control inputs of the second digital multiplier, are connected respectively to the second bit outputs of the memory unit and the second the output of the second delay element, and the output is connected to the second information input of the recorder, the input of the fourth delay element is connected to the output of the first the differentiation unit, the output of the third element OR is connected to the information input of the fourth key, and the input and output of the video amplifier, respectively, are connected to the output of the fourth key and the second input of the third element OR.