SU1390802A2 - Device for receiving bipolar multilevel signals - Google Patents

Description

(61) 951719

(21) 4127568 / 24-04

(22) 02.10.8b

(46) 04.23.88. Bul № 15 (72) G, A.Genii and S./ (. Kozlov

(53) 621.394.62 (088.8)

(56) USSR Author's Certificate No. 951719, cl. H 04 B 1/06, 1981.

(54) DEVICE FOR ACCEPTANCE OF BIPOLAR MULTILEVEL CHRHAJiOB

(57) The invention relates to the transmission of discrete signals. The purpose of the invention is to improve the noise immunity. The device contains a block of memory 1, a block of 2 multiplications of the signals, a controlled divider 3, a comparator 4, a register 5, keys 6 and 9, an integrator 7, a buffer amplifier 8, a resistive divider

10, a trigger 13, a clock generation unit 14. Key 12 and element 11 are introduced. The reference signal is generated from a large signal using an integrator 7, which provides a reference voltage proportional to the average absolute value of the information signal (IC) at the instant of reference. Interference and distortion of the signal have a zero average value and therefore do not affect the formation of the reference signal if they are superimposed on a large IC value. To eliminate the non-optimality of the threshold at small values of the IC, which correspond to information zeros in the device, integrator 7 is disconnected from the rectified IC and connected via a resistor to the zero bus. Thus, small values of the rectified signal, distorted by noise and interference, are replaced by a zero value. This eliminates the effect of interference and distortion on the threshold level. 3 il.

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The invention relates to the field of discrete signal transmission, can be used when receiving bipolar multi-level signals, and is an improvement to the device according to the author. No. 951719.

The purpose of the invention is to increase the fire safety.

Figure 1 shows the structural and electrical circuit diagram of the device; Fig. 2 shows a structural electrical circuit of a memory unit; FIG. 3 shows a structural-electrical circuit of a unit for forming clock pulses.

The device contains a memory block 1 a block 2 of signal multiplication, control. splitter 3, comparator 4, register 5, first key 6, integrator 7, buffer amplifier 8, second key 9, resistive divider 10, element 11, third key 12, trigger 13 and block 14 for generating clock pulses, block 1 the memory contains the first operandion amplifier 15, the switch 16, the capacitor 17 and the second operational amplifier 18, and the block 14 for forming the clock pulses contains the inverter 19, the trigger 20, the register 21, the element 22, the elements 23 and 24 with inverse outputs and inverter 25,

The device works as follows.

Pulse sequences from the pulse generators are supplied to the inputs of the clock shaping unit 14. In the initial state, the keys 6 and 9 are closed, the transmission coefficient of the controlled divider 3 is 1, the trigger 13 is set to the zero state at its output zero

The multi-level information signal is fed to the first input of the memory unit 1, to the second input of which comes from the output of the clock-frequency forming unit 14. When a clock pulse arrives in memory 1, gating of the input signal and storing it is performed. From the output of block 1 of memory, the signal is fed to the first input of block 2 of signal multiplication. Upon receipt at its second input from the trigger 13 logical zero, the transmission coefficient of the signal multiplication unit 2 is equal to

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1, when entering logical unit - minus 1,

When the flip-flop 13 is set to its initial position, its output to the second input of the signal multiplying unit 2 is given a logical zero, and the output of the block; and the signal multipliers 2 set the same signal as at the input. Since, in the absence of a clock pulse, the second key 9 is closed, the first input of the comparator 4 is supplied with a zero threshold through a resistive divider 10, From the output of the signal multiplying unit 2 through a controlled divider 3, whose transmission coefficient is 1 in the absence of a clock pulse, the information signal is received to the second input of comparator 4, where it is compared with the zero threshold. As a result of this comparison, the sign of the information signal is determined, which is written on the leading edge of the clock frequency pulse into the trigger 13. With a negative signal from the output of memory block 1 to the input of signal multiplication block 2, a trigger zero is written to the trigger 13, resulting in the transmission coefficient of the signal multiplication unit 2 is set to 1, and the output of the signal multiplication unit 2 is set to a negative level equal to the input one. With a positive signal at the input of the signal multiplying unit 2, the trigger 13 records a logical unit, which sets the transfer ratio of the signal multiplication unit 2 to 1, as a result of which, in this case, the output of the signal multiplication unit 2 becomes negative, equal to the absolute value of the input. Thus, in block 2 of the signal multiplication, the signals are rectified in the negative range of values. At the time the first frequency element arrives at the first input of the 11th element and if there is an informational 1 coming from the output of the register 5 to the second input of the 11th element, its output a pulse appears that opens the first switch 6, charging the capacitor of the integrator 7, which stores the reference signal for generating comparison thresholds. The time constant of the integrator 7 is chosen so that if a random sequence of information symbols is received, the oscillations of the rectified value of the received signal averaged by the integrator 7 relative to its average value would be insignificant. At the time of arrival of the clock frequency, the third key 12 is opened by discharging the capacitor of the integrator 7.

The reference signal through the buffer amplifier 8 and the second key 9, opened by a clock pulse, arrives at the first input of the comparator 4, the second input of which through a controlled divider 3 receives a gated signal from the output of the signal multiplication unit 2. In comparator 4, the reference value of the information signal at the time of gating and the threshold signal is compared. The ratio of the threshold to the average value of the information signal sample module can vary over a wide range by varying the transmission ratios of the controlled divider 3, as well as by changing the duration of the clock pulses.

When the first clock pulse arrives, the comparison result is written to register 5.

If necessary, comparing the signal with another threshold, i.e. with a different value of this ratio, another clock pulse can be applied to the controlled divider 3 with a delay relative to the first pulse. If in order to make a decision on the transmitted symbol, it is necessary to compare the signal with several threshold values, which accordingly increases the number of controlled inputs of the controlled divider 3 and the outputs of the clock generating unit 14, and the clock pulses for the different controlled inputs of the controlled divider 3 must be time shifted and the signal is compared with different thresholds alternately.

The result of the comparison with the output of the comparator 4 is fed to the input of the register 5, the second input of which receives the clock frequency from the clock pulse generation unit 14, the value of which depends on the number of comparisons to be made. Rezul0

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Comparison data from the output of comparator 4 are recorded in various memory elements of register 5. After the comparison with all required threshold values has been obtained, memory 1 records the new information value of the input signal at the moment of arrival of the next pulse.

At the end of each analysis interval of the sampled value of the signal, the trigger 13 is reset to its original state.

The formation of the reference signal is carried out from the rectified signal with the help of an integrator, which must provide a reference voltage proportional to the average absolute value of the information signal at the time of reference. Interference and distortion of the signal have a zero average value and therefore do not affect the formation of the reference signal if they are superimposed on a large value of the information signal. In case the information value is zero, both positive and negative interference values after rectification have the same sign and can further increase the voltage at the integrator output. This deviation of the reference signal from the average value increases as the average amplitude of the interference increases, which leads to a violation of the threshold in the device. To eliminate the non-optimality of the threshold at low information signal values, which correspond to information zeros in the device, the integrator is disconnected from the rectified information signal and the integrator is connected to the zero bus via a resistor. Thus, small values of the rectified signal, distorted by noise and interference of the communication channel, are replaced by a zero value, thereby eliminating the effect of interference and distortion on the threshold level (reference signal). As a result, the device provides higher noise immunity of reception with increased values of interference and signal distortion in the communication channel.

Claims (1)

Invention Formula A device for receiving bipolar multi-level signals auth.St. five No. 951719, characterized in that, for the purpose of jamming noise immunity, a third key and an AND element are introduced, with the fifth output of the clock shaping unit connected to the second input of the second key through the AND element, the second input Phi2.2 RigZ which is connected to the register output, and the seventh clock of the pulse shaping unit is connected to the first input of the third key, the second input and output of which are connected respectively to the output of the integrator and the common bus.