CN107799043B - GOA circuit detection method and system and electronic equipment - Google Patents
GOA circuit detection method and system and electronic equipment Download PDFInfo
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- CN107799043B CN107799043B CN201711160572.6A CN201711160572A CN107799043B CN 107799043 B CN107799043 B CN 107799043B CN 201711160572 A CN201711160572 A CN 201711160572A CN 107799043 B CN107799043 B CN 107799043B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
Abstract
The invention discloses a detection method, a system and electronic equipment of a GOA circuit, wherein the method comprises the steps of reading and storing a standard time sequence of clock signals of the GOA circuit and a phase relation between each two clock signals; detecting the time sequence of the clock signal actually output by the GOA circuit, comparing the time sequence of each clock signal with a standard time sequence and judging whether the time sequences are consistent; when the timing of the clock signal actually output by the GOA circuit does not coincide with the standard timing, the standard timing is output. The invention solves the problem of black screen caused by disordered time sequence of the display panel when the electrostatic environment or signals are unstable, and improves the stability of the display panel.
Description
Technical Field
The present invention relates to the field of GOA circuit detection, and in particular, to a detection method and system for a GOA circuit, and an electronic device.
Background
When a GOA (gate Drive On array) circuit in an existing display panel is in an electrostatic environment or a signal source is unstable, a short-time GOA circuit timing sequence is easily disordered, so that the GOA circuit is disordered, overcurrent protection of a level converter is caused, and the problem that the display panel is dark in a short time is caused.
Disclosure of Invention
The invention mainly provides a method and a system for detecting a GOA circuit and electronic equipment, and aims to solve the problem that a display panel is dark due to the current time sequence disorder of the GOA circuit.
In order to solve the technical problems, the invention adopts the technical scheme that: the detection method of the GOA circuit is provided, and comprises the following steps:
reading the standard time sequence of the clock signals of the GOA circuit and the phase relation between each clock signal from the microcontroller through the configuration unit, and storing;
detecting the time sequence of the clock signal actually output by the GOA circuit through a detection unit, comparing the time sequence of each clock signal with the standard time sequence in the configuration unit and judging whether the time sequences are consistent with the standard time sequence in the configuration unit; and
when the detecting unit detects that the time sequence of the clock signal actually output by the GOA circuit is not consistent with the standard time sequence in the configuration unit, the standard time sequence of the clock signal is obtained from the configuration unit through the processing unit and output.
In order to solve the technical problem, the invention adopts another technical scheme that: the detection system of the GOA circuit comprises:
the configuration unit is used for reading the standard time sequence of the clock signals of the GOA circuit and the phase relation between each clock signal from the microcontroller and storing the standard time sequence and the phase relation;
the detection unit is connected with the configuration unit and used for detecting the time sequence of the clock signal actually output by the GOA circuit, comparing the time sequence of each clock signal with the standard time sequence in the configuration unit and judging whether the time sequences are consistent or not; and
and the processing unit is connected with the detection unit, and when the detection unit detects that the time sequence of the clock signal actually output by the GOA circuit is not consistent with the standard time sequence in the configuration unit, the processing unit acquires the standard time sequence of the clock signal from the configuration unit and outputs the standard time sequence.
The invention has the beneficial effects that: the method, the system and the electronic equipment for detecting the GOA circuit detect the time sequence of the clock signal actually output by the GOA circuit, compare the time sequence with the time sequence of the standard clock signal, and acquire and output the standard time sequence of the clock signal when the time sequence of the clock signal actually output by the GOA circuit is inconsistent with the time sequence of the standard clock signal, so that the problem of black screen of a display panel caused by disordered time sequences is avoided, and the stability of the display panel is improved.
Drawings
FIG. 1 is a block diagram of a detection system for a GOA circuit according to the present invention;
FIG. 2 is a block schematic diagram of the detection unit of FIG. 1;
fig. 3 is a schematic flow chart of the detection method of the GOA circuit according to the present invention;
fig. 4 is a schematic structural diagram of the electronic device of the present invention.
Detailed Description
Fig. 1 is a block diagram of a detection system of a GOA circuit according to the present invention. As shown in fig. 1, the detection system 1 of the GOA circuit of the present invention includes a configuration unit 11, configured to read and store a standard timing of clock signals of the GOA circuit and a phase relationship between each clock signal from a microcontroller;
the detection unit 12 is connected to the configuration unit 11 and configured to detect a timing sequence of the clock signal actually output by the GOA circuit, compare the timing sequence of each clock signal with a standard timing sequence in the configuration unit 11, and determine whether the timing sequences are consistent;
and the processing unit 13 is connected with the detection unit 12, when the detection unit 12 detects that the timing of the clock signal actually output by the GOA circuit does not accord with the standard timing in the configuration unit 11, the processing unit 13 acquires the standard timing of the clock signal from the configuration unit 11 and outputs the standard timing, and when the detection unit 12 detects that the timing of the clock signal actually output by the GOA circuit accords with the standard timing in the configuration unit 11, the processing unit 13 outputs the standard timing.
The detecting unit 12 includes a plurality of detecting units 121, and the plurality of detecting units 121 are configured to detect a clock signal actually output by the GOA circuit. The detecting unit 12 further includes a delay unit 122, the delay unit 122 is connected to the detecting unit 121, and when the detecting unit 121 detects that the timing of the clock signal actually output by the GOA circuit is consistent with the standard timing in the configuring unit 11, the delay unit 122 delays the timing of the clock signal actually output by the GOA circuit and outputs the standard timing of the clock signal.
The time sequence of the clock signal actually output by the GOA circuit is compared with the standard time sequence in the configuration unit 11, specifically, the parameter of the actual time sequence is compared with the parameter of the standard time sequence, where the parameter includes the number of high levels and low levels of the clock signal, the time for the low level to jump into the high level, the time for the high level to jump into the low level, the widths of the high level and the low level, and the pulse width and the duty ratio of the clock signal. In this embodiment, a memory 111 is disposed in the configuration unit 11 and is used for storing parameters of the standard timing of the clock signal of the GOA circuit, and the delay unit 122 is a shift register.
Fig. 2 is a block diagram of a detection unit in the detection system of the GOA circuit according to the present invention. As shown in fig. 2, the detecting unit 12 includes a plurality of detecting units 121 and a delay unit 122. The normal clock signal of the GOA circuit includes CK1 and CK2 … CKn, where n is a natural number, and when detecting the timing of the clock signal actually output by the GOA circuit, each detecting unit 121 correspondingly detects the CK1 and CK2 … CKn actually output by the GOA circuit, and compares the timing and the phase relationship thereof with the standard CK1 and CK2 … CKn. Specifically, the CK1 detecting unit first detects whether the clock signal CK1 is at a rising edge, if not, waits for the next rising edge, and if so, represents the beginning of a period, and starts to record relevant parameters of the clock signal CK1, such as the number of high and low levels of the clock signal CK1, the time for the low level to jump to the high level, the time for the high level to jump to the low level, the widths of the high and low levels, and the pulse width and duty ratio of the CK1, and compares these parameters with the parameters of the standard timing stored in the configuration unit 11. Meanwhile, the CK2 detecting unit detects whether the clock signal CK2 is at a rising edge, if not, waits for the next rising edge, if so, represents the beginning of a period, and starts to record the number of high and low levels of the clock signal CK2, the time for the low level to jump to the high level, the time for the high level to jump to the low level, the widths of the high and low levels, and the pulse width and duty ratio of the CK2, and compares these parameters with the parameters of the standard timing stored in the configuration unit 11. In the same manner, the actual timing parameters of the clock signals CK3-CKn are simultaneously detected and compared with the standard timing parameters in the configuration unit 11.
In one period, if the actual timing parameter of any one of the clock signals CK1-CKn is different from the standard timing parameter, the detecting unit 121 determines that the timing of the GOA circuit is disordered, and the detecting unit 121 sends an abnormal indication signal to the processing unit 13. After receiving the abnormal indication signal, the processing unit 13 performs a true/false determination, and if the determination is true, the processing unit 13 obtains the standard time sequence from the configuration unit 11 to replace the currently actually output time sequence and outputs the standard time sequence; if the determination is false, the processing unit 13 will be connected to the delay unit 122 of the detection unit 12 to delay and output the clock signal. If the actual timing parameter of each of the clock signals CK1-CKn is the same as the standard timing parameter, the detecting unit 121 determines that the timing of the GOA circuit is normal, and the delay unit 122 delays to output the clock signal.
Fig. 3 is a schematic flow chart of the detection method of the GOA circuit according to the present invention. The method comprises the following steps:
step S1: the standard timing of the clock signals of the GOA circuits and the phase relationship between each clock signal are read from the microcontroller by the configuration unit 11 and stored.
In the present embodiment, a memory 111 is disposed in the configuration unit 11 for storing the standard timing of the clock signals of the GOA circuits and the phase relationship between each clock signal.
Step S2: the timing of the clock signal actually output by the GOA circuit is detected by the detection unit 12, and the timing of each clock signal is compared with the standard timing in the configuration unit 11 to determine whether they are consistent, if they are not consistent, the process goes to step S3, and if they are consistent, the process goes to step S4.
The time sequence of the clock signal actually output by the GOA circuit is compared with the standard time sequence in the configuration unit 11, specifically, the parameters of the actual time sequence are parameters of the standard time sequence, and the parameters include the number of high levels and low levels of the clock signal, the time for the low level to jump into the high level, the time for the high level to jump into the low level, the widths of the high level and the low level, and the pulse width and the duty ratio of the clock signal.
Step S3: the standard timing of the clock signal is acquired from the configuration unit 11 by the processing unit 13 and output.
Step S4: the standard timing is output by the processing unit 13.
Wherein, step S2 includes:
the timing of the clock signal actually output by the GOA circuit is detected by the detecting units 121, and each detecting unit 121 is used for detecting a clock signal actually output by the GOA circuit.
Wherein, step S4 includes:
when the detecting unit 121 detects that the timing of the clock signal actually output by the GOA circuit is consistent with the standard timing in the configuration unit 11, the timing of the clock signal actually output by the GOA circuit is delayed by the delay unit 122 and provided to the processing unit 13.
In the embodiment, the delay unit 122 is a shift register.
Please refer to fig. 4, which is a schematic structural diagram of an electronic device according to the present invention. The electronic device 2 comprises a microcontroller 3 and a timing controller 4, wherein the timing controller 4 is used for reading and storing a standard timing sequence of clock signals of the GOA circuit 5 and a phase relationship between each clock signal from the microcontroller 3, the timing controller 4 is also used for detecting a timing sequence of the clock signals actually output by the GOA circuit, comparing the timing sequence of each clock signal with the standard timing sequence and judging whether the timing sequence is consistent with the standard timing sequence, when the detecting unit 12 detects that the timing sequence of the clock signals actually output by the GOA circuit 5 is consistent with the standard timing sequence, the timing controller 4 outputs the standard timing sequence, and when the detecting unit 12 detects that the timing sequence of the clock signals actually output by the GOA circuit is not consistent with the standard timing sequence in the configuration unit 11, the processing unit 13 acquires the standard timing sequence of the clock signals from the configuration unit 11 and. The electronic device 2 is a display device, and the display device may be an LCD or an OLED. Other devices and functions of the electronic equipment are the same as those of the existing electronic equipment, and are not described in detail herein.
The method, the system and the electronic equipment for detecting the GOA circuit detect the time sequence of the clock signal actually output by the GOA circuit, compare the time sequence with the time sequence of the standard clock signal, and acquire and output the standard time sequence of the clock signal when the time sequence of the clock signal actually output by the GOA circuit is inconsistent with the time sequence of the standard clock signal, so that the problem of black screen of a display panel caused by disordered time sequences is avoided, and the stability of the display panel is improved.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A detection method of a GOA circuit is characterized by comprising the following steps:
reading the standard time sequence of the clock signals of the GOA circuit and the phase relation between each clock signal from the microcontroller through the configuration unit, and storing;
detecting the time sequence of the clock signal actually output by the GOA circuit through a detection unit, comparing the time sequence of each clock signal with the standard time sequence in the configuration unit and judging whether the time sequences are consistent with the standard time sequence in the configuration unit; and
when the detecting unit detects that the time sequence of the clock signal actually output by the GOA circuit is inconsistent with the standard time sequence in the configuration unit, the detecting unit sends an abnormal indicating signal to the processing unit, the processing unit judges whether the clock signal is true or false, and if the clock signal is true, the processing unit acquires the standard time sequence of the clock signal from the configuration unit and outputs the standard time sequence; if the clock signal is false, the processing unit delays the time delay unit connected to the detection unit and outputs the clock signal.
2. The detecting method of the GOA circuit according to claim 1, wherein detecting the timing of the clock signal actually output by the GOA circuit by a detecting unit and comparing the timing of each clock signal with a standard timing in the configuration unit, further comprises:
and when the detecting unit detects that the time sequence of the clock signal actually output by the GOA circuit is consistent with the standard time sequence in the configuration unit, outputting the standard time sequence through the processing unit.
3. The detecting method of the GOA circuit according to claim 1, wherein detecting the timing of the clock signal actually output by the GOA circuit by a detecting unit comprises:
the time sequence of the clock signal actually output by the GOA circuit is detected through a plurality of detecting units, and each detecting unit is used for detecting one clock signal actually output by the GOA circuit.
4. The method of claim 1, wherein outputting, by a processing unit, the standard timing when the detecting unit detects that a timing of a clock signal actually output by the GOA circuit coincides with the standard timing in the configuring unit, comprises:
and when the detecting unit detects that the time sequence of the clock signal actually output by the GOA circuit is consistent with the standard time sequence in the configuration unit, the time sequence of the clock signal actually output by the GOA circuit is delayed by the delay unit and is provided for the processing unit.
5. A detection system for a GOA circuit, comprising:
the configuration unit is used for reading the standard time sequence of the clock signals of the GOA circuit and the phase relation between each clock signal from the microcontroller and storing the standard time sequence and the phase relation;
the detection unit is connected with the configuration unit and used for detecting the time sequence of the clock signal actually output by the GOA circuit, comparing the time sequence of each clock signal with the standard time sequence in the configuration unit and judging whether the time sequences are consistent or not; and
the processing unit is connected with the detection unit, when the detection unit detects that the time sequence of the clock signal actually output by the GOA circuit is inconsistent with the standard time sequence in the configuration unit, the detection unit sends an abnormal indication signal to the processing unit, the processing unit performs true and false judgment, and if the time sequence is true, the processing unit acquires the standard time sequence of the clock signal from the configuration unit and outputs the standard time sequence; if the clock signal is false, the processing unit delays the time delay unit connected to the detection unit and outputs the clock signal.
6. The detection system of a GOA circuit according to claim 5, wherein when the detection unit detects that the timing of the clock signal actually output by the GOA circuit coincides with a standard timing in the configuration unit, the processing unit outputs the standard timing.
7. The detecting system of claim 5, wherein the detecting unit comprises a plurality of detecting units, each detecting unit is configured to detect a clock signal actually output by the GOA circuit.
8. The detecting system of claim 7, wherein the detecting unit further comprises a delay unit, the delay unit is connected to the detecting units, and when the detecting unit detects that the timing of the clock signal actually output by the GOA circuit is consistent with the standard timing in the configuring unit, the delay unit delays the timing of the clock signal actually output by the GOA circuit and outputs the standard timing of the clock signal.
9. The detection system of the GOA circuit according to claim 8, wherein said configuration unit is provided with a memory, said memory stores therein standard timing parameters, said parameters including the number of high and low levels of the clock signal, the time for the low level to jump to the high level, the time for the high level to jump to the low level, the widths of the high and low levels, the pulse width and duty ratio of the clock signal, and said delay unit is a shift register.
10. An electronic device is characterized in that the electronic device comprises a microcontroller and a time schedule controller connected with the microcontroller, the time schedule controller is used for reading and storing a standard time sequence of clock signals of a GOA circuit and a phase relation between each clock signal from the microcontroller, the time schedule controller is also used for detecting the time sequence of the clock signals actually output by the GOA circuit, comparing the time sequence of each clock signal with the standard time sequence and judging whether the time sequence is consistent with the standard time sequence, when the time sequence of the clock signals actually output by the GOA circuit is consistent with the standard time sequence, the time schedule controller outputs the standard time sequence, when a detection unit detects that the time sequence of the clock signals actually output by the GOA circuit is not consistent with the standard time sequence in a configuration unit, a detection unit sends an abnormal indication signal to a processing unit, and the processing unit judges whether the clock signals are consistent with the standard time sequence, if true, acquiring the standard time sequence of the clock signal from the configuration unit through the processing unit and outputting the standard time sequence; if the clock signal is false, the processing unit delays the time delay unit connected to the detection unit and outputs the clock signal.
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| CN109036309A (en) * | 2018-08-01 | 2018-12-18 | 深圳市华星光电技术有限公司 | Sequence controller and its time-series rules method, liquid crystal display |
| CN109243347B (en) * | 2018-10-31 | 2020-07-28 | 合肥鑫晟光电科技有限公司 | Detection circuit of gate driver and display device |
| CN110648617B (en) * | 2019-09-29 | 2023-02-28 | 成都天马微电子有限公司 | Display device, detection method and display system |
| CN111161664B (en) * | 2020-02-13 | 2023-04-07 | Tcl华星光电技术有限公司 | Display device and terminal |
| CN111986603B (en) * | 2020-08-10 | 2022-09-09 | 深圳市华星光电半导体显示技术有限公司 | Display device and electronic apparatus |
| CN114898719B (en) * | 2022-03-24 | 2023-05-30 | Tcl华星光电技术有限公司 | Clock signal conditioning circuit and method, display panel and display device |
| CN114863892A (en) * | 2022-05-12 | 2022-08-05 | 海宁奕斯伟集成电路设计有限公司 | Anti-electrostatic interference device and method and screen logic board |
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| CN105869591A (en) * | 2016-05-31 | 2016-08-17 | 深圳市华星光电技术有限公司 | Drive circuit and liquid crystal display device |
| CN106228944B (en) * | 2016-10-12 | 2019-02-01 | 深圳市华星光电技术有限公司 | Level shift circuit and liquid crystal display panel |
| CN106782244B (en) * | 2017-01-03 | 2020-11-13 | 京东方科技集团股份有限公司 | Test method and test device for touch display screen |
| CN107068092B (en) * | 2017-05-04 | 2019-11-01 | 京东方科技集团股份有限公司 | A kind of electrostatic protection method, device and liquid crystal display |
| CN107240381B (en) * | 2017-07-31 | 2019-11-26 | 京东方科技集团股份有限公司 | A kind of display methods and display device of display device |
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