JP4900031B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus that tests a device under test such as a semiconductor device, and particularly relates to a configuration having a calibration function for adjusting skew between a plurality of drivers.

  2. Description of the Related Art Conventionally, in a semiconductor test apparatus that performs a test by outputting a test signal to an object to be tested (hereinafter referred to as a DUT) such as a semiconductor device, the test signal for testing the DUT is generated as a signal such as a pattern generator. A test corresponding to the content of the test signal is performed by generating the test signal and applying the test signal to the DUT connected to the test head via a timing adjustment unit, a driver, or the like.

  Further, the semiconductor test apparatus has a calibration function for adjusting the skew generated between a plurality of drivers by transmitting each circuit and transmission path in the apparatus when testing the DUT. By adjusting the skew with this calibration function, the timing at which the test signal is output from each driver to the DUT coincides, and the determination of the output signal from the DUT, the processing based on the test result, and the like are accurately performed with good timing.

  In the semiconductor test apparatus described in Patent Document 1 below, a reference driver DRa that outputs a signal with a reference waveform whose voltage level change timing is a reference, a driver DRb that outputs a signal with a waveform obtained by inverting the reference waveform, A delay element that is provided in a preceding stage of the driver DRb and delays the output timing of the signal output from the driver DRb in a changeable manner. Then, as shown in FIG. 8, the calibration board 50 generates a combined waveform by combining the output signal of the reference driver DRa and the output signal of the driver DRb. Since this combined waveform is always a constant voltage if the delays of the drivers DRa and DRb are the same, the voltage of the combined waveform is detected by the comparator CP0, and the delay elements 220 and 222 adjust the delay amount so that it becomes a constant voltage. The skew is adjusted by adjusting (see, for example, Patent Document 1).

JP 2006-105636 A (FIG. 1)

  Further, in the conventional semiconductor test apparatus, the skew generated between a plurality of drivers is adjusted by the calibration function as follows. FIG. 9 is an explanatory diagram showing a configuration of a signal output unit in the conventional semiconductor test apparatus 200. In the conventional semiconductor test apparatus 200, the output sections of a plurality of drivers DR1 and DR2 that output test signals to the DUT are connected by a transmission path T1. When the calibration function is executed, the output section of the driver DR1 and the output section of the driver DR2 are connected using the relays RL1 and RL2 provided on the transmission path T1, but at this time, the relay (switch) RL3 is opened. As a result, the driver DR2 is disconnected.

  When the calibration function is executed, for example, a converter A / D1 (A / D converter) connected to the driver DR1 transmits a signal output from the driver DR1 through the transmission path T1 and outputs the driver DR2. The time (TDR) until reaching the part and returning after reflection is measured. Thereby, the electrical length (Tpd = TDR / 2) of the transmission path T1 can be calculated by the time domain reflection method.

  Next, as shown in FIG. 10, the relay (switch) RL3 is closed to bring the driver DR2 into a connected state, and the 50 Ω termination is made in the same manner as the driver DR1, and is actually generated by a signal generator (not shown) in the semiconductor test apparatus 200. A test signal is output from the driver DR1. At this time, the test signal output from the driver DR1 is transmitted through the transmission path T1 and input to the converter A / D2 (A / D converter) connected to the output unit of the driver DR2. Based on the timing at which the test signal generated by the same signal generator is output from the driver DR2, the difference between the reference timing and the timing at which the test signal output from the driver DR1 reaches A / D2 is calculated as TPD.

When the output of the driver DR1 is output earlier than the output of the driver DR2, the skew between the driver DR1 and the driver DR2 is output from the driver DR1 due to the electrical length of the transmission path T1 between the driver DR1 and the driver DR2. Since it is a time difference obtained by subtracting the time (TPD) until the test signal reaches A / D2, it is calculated by the following equation.

Skew = TDR / 2-TPD

The skew thus calculated is set in the delay adjustment circuit DL1 to adjust the skew.

  However, in such a calibration function of the semiconductor test apparatus 200 in the prior art, the output terminal of the A / D 2 and the driver DR 2 is switched by the relay RL 3 to transmit the transmission path T 1 and output the signal twice. Since the delay time TDR and the signal delay TPD are measured separately, there is a problem that the measurement time for calculating the skew becomes long.

  Further, when calculating the signal delay TPD, it is necessary to adjust the skew between the A / D 2 for measuring the timing and the driver DR2, and the measurement time becomes longer depending on the time required for the adjustment work.

  Furthermore, in the process of calculating the delay time TDR and the signal delay TPD, the slew rate increases at the rising edge of the signal waveform input to A / D1 and A / D2, that is, the accuracy increases as the signal waveform rises sharply. It is said that the rise of the signal becomes slow due to attenuation when transmitting back and forth through the transmission path T1, and the output capacity when the driver DR2 is Hi-z, and the measurement accuracy deteriorates. There was a problem.

  In the semiconductor test apparatus described in Patent Document 1, the waveforms of the drivers DR0 and DR1 are inverted from each other. However, if the transition states such as the rising and falling slew rates do not match, the delay is the same. However, there is a problem that the synthesized waveform does not become a constant voltage.

  Furthermore, it is practically difficult to synthesize signals from a plurality of drivers that adjust skew and adjust all of them to a single constant voltage, and the wiring length for transmitting these signals in calibration is difficult. If an error occurs, there is a problem that the skew can no longer be adjusted accurately.

  Accordingly, an object of the present invention is to provide a semiconductor test apparatus capable of reducing the time for adjusting the skew between a plurality of drivers and accurately calculating the skew with less error.

In order to achieve the above-described problems, a semiconductor test apparatus according to the present invention includes a signal generating means for generating a test signal for testing an object to be tested, and a test signal generated by the signal generating means. First and second drivers to be output to the test object, a transmission path for connecting the first and second drivers, and a test signal are simultaneously output from the first and second drivers via the transmission path. A driver control unit for controlling the first and second drivers so that the first driver outputs a test signal in the first driver, and a test signal output from the second driver arrives. A first timing measuring unit that measures the first arrival timing, a second output timing at which a test signal is output in the second driver, and the first A second timing measuring unit that measures a second arrival timing at which the test signal output from the driver has arrived; and the first and second timings based on the timings measured by the first and second timing measuring units. A skew calculating unit that calculates a skew between two drivers, and a timing adjusting unit that adjusts a timing at which a test signal is output from the first driver based on the skew calculated by the skew calculating unit. The path includes a relay that switches between a connection state and a non-connection state of the first and second drivers.

With such a configuration, the timing measurement unit measures the output timing and the arrival timing in each of the drivers by outputting the test signal simultaneously once between the first driver and the second driver. Since the skew is calculated, the number of times of outputting a signal is reduced, and the time for adjusting the skew generated between a plurality of drivers can be shortened. In addition, since the test signals output from each driver are signals that have been transmitted only one way along the transmission path, the influence of rise-up roundoff (response delay) due to attenuation or the like when reciprocating the transmission path as in TDR measurement is reduced. Therefore, it is possible to accurately calculate the skew with less measurement error.

  In the above-described semiconductor test apparatus, the skew calculation unit calculates a first time difference between a first output timing measured by the first timing measurement unit and a first arrival timing. Calculating means; second time difference calculating means for calculating a second time difference between the second output timing measured by the second timing measuring section and the second arrival timing; and And a time difference calculation unit that calculates the skew by dividing the difference between the first and second time differences calculated by the two time difference calculation means by two.

  In the semiconductor test apparatus described above, the skew calculation unit divides the sum of the first and second time differences calculated by the first and second time difference calculation units by 2, and the test signal is transmitted to the transmission path. It is good also as providing the delay calculating part which calculates the delay which arises when transmitting.

  The above-described semiconductor test apparatus may further include a relay that switches between the connected state and the disconnected state of the first and second drivers.

  According to the semiconductor test apparatus of the present invention, it is possible to shorten the time for adjusting the skew between a plurality of drivers, and to obtain an effect that the skew can be accurately calculated with less error.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of an output portion around a driver that outputs a test signal to a DUT via a test head or the like in a semiconductor test apparatus 100 that is an embodiment of a semiconductor test apparatus according to the present invention. It is explanatory drawing.

  The semiconductor test apparatus 100 includes a signal generator 110 that generates a test signal for testing the DUT. The signal generator 110 is, for example, a pattern generator (ALPG), and the test signal generated here is transmitted from each of the circuits and transmission paths in the apparatus and output from the drivers DR1 and DR2.

  In addition, the semiconductor test apparatus 100 includes a control unit 120 that outputs and controls a control signal or the like to each circuit in the apparatus during an actual test or execution of a calibration function. The control unit 120 controls each circuit in the apparatus at the time of the test and outputs a control signal to the drivers DR1 and DR2 and the converters A / D1 and A / D2 at the time of executing the calibration function to control the test signal. A process for transmitting and outputting the transmission path T1, and a process for measuring the timing at which test signals are input and output are performed.

  In addition, the control unit 120 performs calculations using data such as timings at which the drivers DR1 and DR2 input / output test signals, and calculates the skew between the drivers DR1 and DR2 and the electrical length of the transmission path T1.

  FIG. 2 is an explanatory diagram showing the configuration of the control unit 120. The control unit 120 is, for example, a CPU or the like, and receives the timing data when the drivers DR1 and DR2 input and output the test signal from the converters A / D1 and A / D2, and calculates the time difference between the rising and falling edges of the signal Extractors 121 and 122 are provided.

  In addition, the control unit 120 includes a subtraction circuit 123 and an addition circuit 124 that calculate the difference and sum of the data of the time differences calculated by the edge extraction units 121 and 122, respectively.

  The control unit 120 performs a process of dividing the difference in time difference data calculated by the subtraction circuit 123 by 2 to calculate the skew between the drivers DR1 and DR2, and the time difference data calculated by the addition circuit 124. A division circuit 126 that performs a process of dividing the sum by 2 to calculate the electrical length of the transmission path T1.

  In the control unit 120, a control signal is output from the control circuit (CPU core) 128 to each circuit described above. A storage device 127 such as a RAM is connected to the control unit 120, and data such as skew and electrical length calculated by the control unit 120 is stored in the storage device 127 based on an access command from the control circuit 128. .

  The semiconductor test apparatus 100 includes drivers DR1 and DR2 that receive the test signal generated by the signal generator 110 and output the test signal to the DUT. The drivers DR1 and DR2 have a function of outputting a test signal generated by the signal generator 110 to the DUT and outputting a test signal for skew adjustment when executing the calibration function.

  The semiconductor test apparatus 100 is connected to each of these drivers DR1 and DR2, and converters A / D1, A / that measure the output timing and arrival timing at which test signals and data are input to and output from the drivers DR1 and DR2. D2 (both are A / D converters). The converters A / D1 and A / D2 are connected to the drivers DR1 and DR2, respectively. As shown in the timing chart of FIG. 5, the test signals are simultaneously output from the drivers DR1 and DR2 through the transmission path T1. The output timings t1 and t2 are measured. The converters A / D1 and A / D2 have arrival timing t4 when the test signal is transmitted through the transmission path T1 and the output of the driver DR1 reaches the driver DR2, and arrival timing t4 when the output of the driver DR2 reaches the driver DR1. Measure.

  The semiconductor test apparatus 100 switches between a transmission path T1 that connects the drivers DR1 and DR2 and transmits signals, and a connection state and a non-connection state between the drivers DR1 and DR2 that are provided on the transmission path T1. Relays RL1 and RL2 are provided. The relays RL1 and RL2 are provided on the transmission path T1. When the drivers DR1 and DR2 output test signals to the DUT during a test, the relays RL1 and RL2 are switched between the drivers DR1 and DR2. Further, when the drivers DR1 and DR2 simultaneously transmit the test signals through the transmission path T1 when the calibration function is executed, the drivers DR1 and DR2 are switched to the connected state.

  The semiconductor test apparatus 100 includes a timing adjustment circuit DL1 connected to a side to which a signal transmitted through the apparatus is input to the driver DR1. The timing adjustment circuit DL1 is connected to a terminal or the like on the side where the test signal is input to the driver DR1, is set based on the skew calculated by the control unit 120, and adjusts the timing at which the test signal is input to the driver DR1. As a result, the driver DR1 has the function of adjusting the skew by matching the timing of outputting the test signal to the DUT with the driver DR2.

  Next, the operation of the semiconductor test apparatus 100 in the present embodiment will be described in detail using the flowchart shown in FIG. First, when the calibration function is executed at a time other than a test in which the DUT is not connected to the test head or the like of the semiconductor test apparatus 100, the relays RL1 and RL2 switch between the drivers DR1 and DR2.

  Step S301: The semiconductor test apparatus 100 performs a process of simultaneously transmitting test signals from the drivers DR1 and DR2 through the transmission path T1. The semiconductor test apparatus 100 outputs a control signal to the drivers DR1 and DR2 by the control unit 120 and controls it so that the test signals are transmitted through the transmission path T1 and are simultaneously output from the drivers DR1 to DR2 and from the drivers DR2 to DR1. .

  At this time, the semiconductor test apparatus 100 outputs test signals from the drivers DR1 and DR2 by the converters A / D1 and A / D2, respectively, and simultaneously outputs them by transmitting the transmission path T1 as shown in FIG. t1 and t2 are measured. Here, the drivers DR1 and DR2 are controlled by the control unit 120 and simultaneously output test signals. However, the test signals generated by the signal generation unit 110 are transmitted to each circuit and transmission path in the apparatus and driver. Since there is a delay time difference between the output from DR1 and DR2 and a skew is generated between the drivers DR1 and DR2, the output timings t1 and t2 are different times as shown in FIG.

  Step S302: The semiconductor test apparatus 100 performs a process of measuring arrival timings t4 and t3 at which the test signals transmitted through the transmission path T1 by the converters A / D1 and A / D2 arrive at the drivers DR1 and DR2. In the semiconductor test apparatus 100, the test signals output simultaneously from the drivers DR1 and DR2 from the drivers DR1 and DR2 in step S301 by the converters A / D1 and A / D2, respectively, transmit the transmission path T1 as shown in FIG. The arrival timings t3 and t4 reaching DR1 are measured.

  Step S303: The semiconductor test apparatus 100 calculates a time difference of signal rise using the data of the output timings t1 and t2 and the arrival timings t3 and t4 measured by the converters A / D1 and A / D2 by the control unit 120. I do. The semiconductor test apparatus 100 performs calculation using the data of the output timing t1 and the arrival timing t4 measured in steps S301 and S302 by the edge extraction unit 121 of the control unit 120, and outputs from the driver DR1 as shown in FIG. A time difference t4-t1 between the rising edge of the test signal and the rising edge of the test signal reaching the driver DR1 is calculated.

  Further, the semiconductor test apparatus 100 performs an operation using the data of the output timing t2 and the arrival timing t3 measured in steps S301 and S302 by the edge extraction unit 122 of the control unit 120, and from the driver DR2 as shown in FIG. A time difference t3-t2 between the rising edge of the output test signal and the rising edge of the test signal reaching the driver DR2 is calculated.

Step S304: In the semiconductor test apparatus 100, the control unit 120 performs a process of calculating a skew between the drivers DR1 and DR2 by using the data of the time difference between the rising edges of the signals of the drivers DR1 and DR2. The semiconductor test apparatus 100 performs an operation using the time differences t4-t1 and t3-t2 of the rise of the signals of the drivers DR1 and DR2 calculated by the control unit 120 in step S303, and calculates a skew according to the following formula.
That is, assuming that the electrical length transmitted through the transmission path T1 is Tpd, as shown in FIGS. 4 (a) and 4 (b),

Time difference Δt41 = t4−t1 = Tpd + Skew
Time difference Δt32 = t3-t2 = Tpd-Skew

Such a relationship is established, and when calculating the skew from this relational expression,

Skew = (Δt41−Δt32) / 2
Tpd = (Δt41 + Δt32) / 2

With such a mathematical formula, the skew is calculated by dividing the difference between the time difference t4-t1 and the time difference t3-t2 by two. Further, the electrical length transmitted through the transmission path T1 is calculated by dividing the sum of the time difference t4-t1 and the time difference t3-t2 by 2. The calculated skew and electrical length data are stored in the storage device 127.

  Step S305: The semiconductor test apparatus 100 performs a process of adjusting the skew by setting the calculated skew in the timing adjustment circuit DL1 by the control unit 120. The semiconductor test apparatus 100 reads the skew data calculated in step S304 by the control circuit 128 of the control unit 120 from the storage device 127, sets the timing adjustment circuit DL1, and adjusts the timing at which the test signal is input to the driver DR1, The skew is adjusted so that the timing at which the test signal is output from the driver DR1 to the DUT matches that of the driver DR2.

  As described above, in the semiconductor test apparatus 100 according to the present embodiment, test signals are transmitted from the drivers DR1 and DR2 through the transmission path T1 and simultaneously output, and the output timings t1 and t2 at this time and the drivers DR1 and DR2 The arrival timings t4 and t3 arrived at are measured. Then, using the data of the output timings t1 and t2 and the arrival timings t3 and t4 at the drivers DR1 and DR2, the time difference between the rising edges of the signals of the drivers DR1 and DR2 is calculated, and further calculation is performed to determine the skew between the drivers DR1 and DR2. Is calculated. The calculated skew is set in the timing adjustment circuit DL1, and the skew is adjusted.

  For this reason, output timings t1, t2 and arrival timings t3, t4 are measured by simultaneously transmitting the test signals from the drivers DR1, DR2 through the transmission path T1 and only once, and using these data. Since the skew and the electrical length are calculated, the number of times that the signal is output and the timing is measured is two times in the conventional method, so that the entire time can be shortened. Further, since the test signal is a signal that is transmitted only one way along the transmission path T1, the occurrence of rounding (response delay) due to attenuation or the like when transmitting back and forth through the transmission path T1 in the conventional method is reduced, and errors are reduced. Thus, the skew can be calculated accurately. Note that the electrical length can be accurately calculated using the data of the output timings t1 and t2 and the arrival timings t3 and t4, and the characteristics of the transmission path T1 can be evaluated.

  Further, the calculated time differences Δt41 and Δt32 in this embodiment are relative time differences measured by the converters A / D1 and A / D2, respectively, and are absolute timings of t1, t2, t3, and t4. I don't need time. Therefore, even if there is a time lag (skew) between the converter A / D1 and the converter A / D2, the target skew of the present embodiment can be measured and calculated. That is, the skew adjustment between the converter A / D1 and the converter A / D2 can be omitted, and the time can be shortened.

  If the timing can be accurately measured by the converters A / D1 and A / D2, the transition states of the signals output from the drivers DR1 and DR2 do not need to match, and the skew can be accurately calculated.

  Here, when the skew between the converter A / D2 connected to the driver DR2 and the driver DR2 is adjusted in advance, not only the skew between the driver DR1 and the driver DR2, but also the converter The skew between A / D1 and converter A / D2 can be calculated simultaneously as follows. FIG. 6 is obtained by adding a timing t11 as a reference for the converter A / D1 connected to the driver DR1 to the timing chart of FIG. 5 in the present embodiment. Since this timing is neither skew adjusted by the output timing of the driver DR1 nor the converter A / D2 (driver DR2), as shown in FIG. 6, it does not coincide with any other timing.

As shown in FIG. 6, the arrival timing t40 of the test signal transmitted from the driver DR2 through the transmission path T1 and reaching the converter A / D1 is delayed by the electrical length of the transmission path T1 with respect to the output timing of the driver DR2. Yes. Therefore, the test signal is output from the driver DR2 to the converter A / D1 at the timing obtained by subtracting the electrical length of the transmission path T1 from the arrival timing t40. The difference between this timing and the reference timing t11 of the converter A / D1 described above becomes a skew between the converter A / D1 and the converter A / D2 (driver DR2). That is, the skew between the converter A / D1 and the converter A / D2 is calculated as follows.

Skew (A / D) = t40−Tpd−t11

In this calculation, the arrival timing t40 and the electrical length of the transmission path T1 may be the values t4 and Tpd already measured and calculated in step S304 on the flowchart of FIG. Since t11 is a reference timing of the converter A / D1 arbitrarily determined before skew adjustment, there is no need to newly measure for skew adjustment between the converter A / D1 and the converter A / D2, It can be obtained only by calculation.

[Other Embodiments]
In the above embodiment, as shown in FIG. 1, two drivers DR1 and DR2 are provided and the skew between these drivers DR1 and DR2 is calculated and adjusted. However, as shown in FIG. In the semiconductor test apparatus 150 provided with the above drivers DR1, DR2,..., The skew between the drivers DR1, DR2,.

  In this semiconductor test apparatus 150, transmission paths for connecting the converters A / D1, A / D2,... Connected to the respective drivers DR1, DR2,. Relays RL1, RL2,... Provided on the transmission path for switching between a connected state and a non-connected state between the drivers DR1, DR2,. Moreover, the edge extraction part in the control part 120 is comprised by the edge extraction parts 121, 122, ... connected according to each converter A / D1, A / D2, ....

  Then, the driver DR2 is used as a reference driver and the other drivers DR1,... Are used as drivers to be calibrated, and the driver DR2 and the drivers DR1,. The process of calculating and adjusting the skew between the driver DR2 and the driver DR1 as described above is executed similarly between the driver DR2 and the drivers DR1,. The skew is adjusted so that the timing at which the test signals are output from the other drivers DR1,.

  In the above-described embodiment, the output timings t1 and t2 and the arrival timings t3 and t4 are measured by the converters A / D1 and A / D2. However, the measurement is not limited to this, and measurement is performed using other circuits and configurations. May be.

  In the above-described embodiment, the transmission path T1 is provided in the semiconductor test apparatus 100. However, the present invention is not limited to this, and the driver DR1, the transmission path T1 is provided by an external device or an external transmission path via an external output terminal. DR2 may be connected. In this case, an external device or an external transmission path is removed from the external output terminal during an actual test, and is connected only when the calibration function is executed.

  Further, in the above-described embodiment, the skew of the drivers DR1 and DR2 that output the test signal to the DUT is adjusted by the calibration function. However, other parts of the device that need to adjust the skew, for example, It can also be used for other types of electronic devices such as logic analyzers and oscilloscopes having a TDR function.

It is explanatory drawing which shows the structure of the semiconductor test apparatus of this embodiment. It is explanatory drawing which shows the structure of the control part of the semiconductor test apparatus of this embodiment. It is a flowchart which shows operation | movement of the semiconductor test apparatus of this embodiment. It is explanatory drawing which shows the time difference of the signal rise of the driver of the semiconductor test apparatus of this embodiment. It is a timing chart which shows the timing which inputs and outputs the test signal of the driver of the semiconductor testing device of this embodiment. It is a timing chart which shows the timing which inputs / outputs the test signal of the driver of the semiconductor test device of other embodiments. It is explanatory drawing which shows the structure of the semiconductor test apparatus of other embodiment. It is explanatory drawing which shows the structure of the semiconductor test apparatus of a prior art. It is explanatory drawing which shows the operation | movement which measures TDR of the semiconductor test apparatus of a prior art. It is explanatory drawing which shows the operation | movement which measures Tpd of the semiconductor test apparatus of a prior art.

Explanation of symbols

100, 150, 200 Semiconductor test equipment DR1, DR2 Driver A / D1, A / D2 converter T1 Transmission path RL1, RL2, RL3 Relay DL1 Timing adjustment circuit 110 Signal generator 120 Controller

Claims (3)

Signal generating means for generating a test signal for testing the device under test;
First and second drivers for outputting a test signal generated by the signal generating means to the test object;
A transmission path connecting the first and second drivers;
A driver controller that controls the first and second drivers so that test signals are simultaneously output from the first and second drivers via the transmission path;
A first timing measuring unit that measures a first output timing at which a test signal is output in the first driver and a first arrival timing at which the test signal output from the second driver arrives;
A second timing measuring unit for measuring a second output timing at which a test signal is output in the second driver and a second arrival timing at which the test signal output from the first driver arrives;
A skew calculating unit that calculates a skew between the first and second drivers based on the timing measured by the first and second timing measuring units;
A timing adjustment unit that adjusts the timing of outputting a test signal from the first driver based on the skew calculated by the skew calculation unit ;
The semiconductor test apparatus , wherein the transmission path includes a relay that switches between a connection state and a non-connection state of the first and second drivers . The semiconductor test apparatus according to claim 1 ,
The skew calculator is
First time difference calculating means for calculating a first time difference between the first output timing measured by the first timing measuring unit and the first arrival timing;
Second time difference calculating means for calculating a second time difference between the second output timing measured by the second timing measuring unit and the second arrival timing;
A semiconductor test apparatus comprising: a time difference calculation unit that calculates the skew by dividing a difference between the first and second time differences calculated by the first and second time difference calculation means by two. The semiconductor test apparatus according to claim 2 ,
The skew calculator is
A delay calculation unit that calculates a delay caused when the test signal is transmitted through the transmission path by dividing the sum of the first and second time differences calculated by the first and second time difference calculation means by 2 A semiconductor test apparatus further comprising:

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