JP2009293930A - Measurement apparatus and testing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a measurement apparatus and a testing apparatus for measuring the delay time in a delay circuit, in a short time. <P>SOLUTION: The measurement apparatus for measuring the delay time in the delay circuit includes: a loop connecting section for connecting an output of the delay circuit to an input of the delay circuit; a loop counting section for counting pulses circulated within a loop circuit, including the delay circuit and the loop connection section; and a reference clock count section for accumulating a plurality of reference clocks, and counting the number of the reference clocks, while the loop counting section counts the predetermined number of the pulses. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a measuring apparatus and a test apparatus. In particular, the present invention relates to a measuring apparatus for measuring a delay time of a delay circuit and a test apparatus including the measuring apparatus.

  A test apparatus for testing a semiconductor generates a timing signal that designates the timing of a change point of a test signal by a delay circuit. The delay circuit delays the reference clock according to the delay setting value designated by the test pattern and generates a timing signal.

  Further, the test apparatus measures an actual delay time for each delay set value in the delay circuit before the test. Then, the test apparatus performs a linearization process for creating a table indicating the correspondence relationship between the actual delay time and the delay set value (for example, Patent Document 1). Further, the delay time of the delay circuit varies depending on the power supply voltage, the ambient temperature, and the like. Therefore, in the linearization process, the test apparatus measures the delay time of the delay circuit a plurality of times and averages the plurality of measurement results for the purpose of removing the influence due to the delay time fluctuation.

JP 2008-53914 A

  However, when the delay time of the delay circuit is measured a plurality of times in this way, the test apparatus must read the measurement result a plurality of times, and must perform an arithmetic process after completing the plurality of measurements. It was. As a result, such a test apparatus may have a long measurement time.

  Then, an object of this invention is to provide the measuring apparatus and test apparatus which can solve said subject. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above problems, in the first embodiment of the present invention, a measuring device for measuring a delay time of a delay circuit, a loop connection unit for connecting an output of the delay circuit to an input of the delay circuit, Counts the number of reference clocks that are accumulated multiple times while the loop count unit counts a predetermined number of pulses, and the loop count unit that counts the pulses circulating in the loop circuit including the delay circuit and the loop connection unit And a reference clock count unit.

  According to a second aspect of the present invention, there is provided a measuring apparatus for measuring a delay time of a delay circuit, wherein an output of the delay circuit is connected to an input of the delay circuit to form a loop circuit including the delay circuit, or a delay A loop connection unit that selects whether to form a loop circuit that does not include a circuit, a pulse that circulates in the loop circuit that includes the delay circuit, and a loop count unit that counts pulses that circulate in the loop circuit that does not include the delay circuit A reference clock count unit that counts the number of reference clocks while the loop count unit counts a predetermined number of pulses for each of the loop circuit including the delay circuit and the loop circuit not including the delay circuit, and the delay circuit Offset storage unit for storing the number of reference clocks counted by the reference clock count unit for a loop circuit not including , To provide a measuring apparatus and a subtraction unit subtracting the number stored in the offset storage unit from the number of reference clock a reference clock count unit has counted the loop circuit including a delay circuit.

  According to a third aspect of the present invention, there is provided a measuring apparatus for measuring a delay time of a delay circuit, a loop connection portion for connecting an output of the delay circuit to an input of the delay circuit, and a reference for counting the number of reference clocks. While the clock count unit and the reference clock count unit count a predetermined number of reference clocks, the number of pulses circulating in the loop circuit including the delay circuit and the loop connection unit is accumulated and counted multiple times. And a loop counting unit.

  According to a fourth aspect of the present invention, there is provided a test apparatus that tests a device under test, a variable delay circuit that outputs an input signal with a delay amount corresponding to a given delay setting value, and a variable delay circuit. A measuring device for measuring a delay time, the measuring device circulating in a loop circuit including the variable delay circuit and the loop connecting unit, the loop connecting unit connecting the output of the variable delay circuit to the input of the variable delay circuit Provided is a test apparatus having a loop count unit that counts pulses and a reference clock count unit that accumulates and counts the number of reference clocks while the loop count unit counts a predetermined number of pulses. .

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows a configuration of a test apparatus 100 according to this embodiment together with a device under test 200. The test apparatus 100 gives a test signal to the device under test 200. The test apparatus 100 tests the device under test 200 by comparing the expected value with the response signal output from the device under test 200 according to the test signal.

  The test apparatus 100 includes a pattern generation unit 122, a timing generator 124, a waveform shaping unit 126, a driver 128, a level comparator 130, a timing comparator 132, and a determination unit 134. The pattern generator 122 specifies a test pattern that specifies the waveform of a test signal to be applied to the device under test 200 and a logical value of a response signal to be output from the device under test 200 in response to the application of the test signal. Generate an expected value pattern. Further, the pattern generator 122 generates timing information indicating the timing of waveform change (edge) of the test signal and the comparison timing between the response signal and the expected value.

  Based on the timing information received from the pattern generator 122, the timing generator 124 generates a timing signal that specifies the timing for transmitting and receiving signals to and from the device under test 200. As an example, the timing generator 124 may generate a timing signal that specifies the timing of the waveform change of the test signal and a timing signal that specifies the comparison timing between the response signal and the expected value.

  The waveform shaping unit 126 generates a test signal obtained by shaping a test pattern with reference to the timing signal supplied from the timing generator 124. As an example, the waveform shaping unit 126 may generate a test signal having a waveform specified by a test pattern and having a waveform whose level changes at the timing of the timing signal.

  The driver 128 supplies the test signal generated by the waveform shaping unit 126 to the device under test 200. The level comparator 130 receives the response signal output from the device under test 200 according to the test signal, and outputs a logic value signal representing a logic value according to the level of the received response signal.

  The timing comparator 132 takes in the logical value represented by the logical value signal output from the level comparator 130 at the timing of the timing signal provided from the timing generator 124. The determination unit 134 compares the logical value captured by the timing comparator 132 with the expected value specified by the expected value pattern generated by the pattern generation unit 122, and outputs a comparison result. For example, when the logical value captured by the timing comparator 132 matches the expected value, the determination unit 134 outputs a comparison result representing a path, and the logical value captured by the timing comparator 132 matches the expected value. If not, a comparison result indicating failure may be output.

  FIG. 2 shows the variable delay circuit 300 and the linearized memory 310 provided in the test apparatus 100 according to the present embodiment, and the measurement apparatus 10 that measures the delay time of the variable delay circuit 300. The test apparatus 100 includes one or a plurality of variable delay circuits 300. For example, the timing generator 124 included in the test apparatus 100 includes a plurality of variable delay circuits 300 for generating timing signals and a plurality of linearized memories 310 corresponding to the variable delay circuits 300.

  The variable delay circuit 300 delays the input signal by a delay amount corresponding to a given delay setting value and outputs the delayed input signal. The linearize memory 310 stores a table in which a plurality of delay designation values designated according to timing information and delay setting values to be given to the variable delay circuit 300 are associated with each other. When the linearized memory 310 receives the delay designation value, it provides the variable delay circuit 300 with a delay setting value corresponding to the received delay designation value.

Furthermore, the test apparatus 100 includes a measurement apparatus 10. The measuring device 10 measures the delay time of the variable delay circuit 300. For example, the measuring apparatus 10 may measure the actual delay time of the variable delay circuit 300 for each of a plurality of delay setting values to be given to the variable delay circuit 300 at the time of calibration performed prior to the test. Then, for example, the measuring apparatus 10 generates a table to be stored in the linearized memory 310 according to the measurement result of the actual delay time of the variable delay circuit 300 for each delay setting value. The measuring apparatus 10 may measure the delay times of the plurality of variable delay circuits 300 provided in the test apparatus 100 by sequentially switching the delay times.

  FIG. 3 shows the configuration of the measurement apparatus 10 according to the present embodiment, together with the variable delay circuit 300 that is the measurement target. The measuring apparatus 10 sequentially gives a plurality of delay setting values to the variable delay circuit 300 to be measured, and measures the delay time of the variable delay circuit 300 for each of the plurality of delay setting values.

  The measuring apparatus 10 includes a setting unit 16, a loop connection unit 20, a pulse input unit 22, a loop count unit 24, a count operation detection unit 26, an end detection unit 28, a reference clock count unit 30, and a control unit. 32, an initialization prohibition unit 34, an offset storage unit 36, a subtraction unit 38, a selection unit 40, and a memory unit 42. The setting unit 16 gives a delay setting value to the variable delay circuit 300 to be measured.

  The loop connection unit 20 connects the output of the variable delay circuit 300 to the input of the variable delay circuit 300 to form a loop circuit. Furthermore, the loop connection unit 20 also forms a loop circuit that does not include the variable delay circuit 300. Whether the loop connection unit 20 connects the output of the variable delay circuit 300 to the input of the variable delay circuit 300 to form a loop circuit including the variable delay circuit 300 or a loop circuit not including the variable delay circuit 300 Select.

  As an example, the loop circuit that does not include the variable delay circuit 300 may be a circuit that bypasses the portion of the variable delay circuit 300 in the loop circuit in which the output of the variable delay circuit 300 is connected to the input of the variable delay circuit 300. That is, the loop circuit that does not include the variable delay circuit 300 is a circuit in which the path excluding the variable delay circuit 300 is shared with the loop circuit in which the output of the variable delay circuit 300 is connected to the input of the variable delay circuit 300. Good. Further, as an example, the loop connection unit 20 may switch the connection between the variable delay circuit 300 and a circuit that bypasses the variable delay circuit 300 using a selector.

  The pulse input unit 22 inputs a pulse to the loop circuit formed by the loop connection unit 20 according to an instruction from the outside, and propagates one pulse in the loop circuit. That is, the pulse input unit 22 circulates one pulse through the loop circuit formed by the loop connection unit 20.

  As an example, the pulse input unit 22 may include a pulse generation unit 44 and an OR circuit 46. The pulse generator 44 generates one pulse in response to an instruction from the outside. The OR circuit 46 is inserted into the loop circuit path formed by the loop connection unit 20, and ORs the signal propagating through the loop path and the pulse generated by the pulse generation unit 44 and outputs the result. Such a pulse input unit 22 can input one pulse into the loop circuit.

  The loop count unit 24 counts the number of circulations of pulses circulating in the loop circuit formed by the loop connection unit 20. As an example, the loop count unit 24 may receive a part of pulses propagating in the loop circuit from a path branched from one point of the loop circuit formed by the loop connection unit 20, and may count the number of received pulses. .

  In the present embodiment, the loop count unit 24 counts the set number of pulses received from the loop circuit, with a set number of pulses that is a predetermined number of pulses being designated from outside. For example, the loop count unit 24 may take the set pulse number as a count value when a count operation start instruction is given, and decrease the count value by 1 each time a pulse is received from the loop circuit. The loop count unit 24 may stop the count operation when the count value reaches zero.

  Further, the loop count unit 24 repeats a counting operation for counting the number of pulses circulating in the loop circuit by a set number of times. As an example, the loop count unit 24 may perform such a counting operation a plurality of times at predetermined intervals.

  The count operation detection unit 26 detects a period during which the loop count unit 24 is performing a count operation for counting pulses circulating in the loop circuit by the number of set pulses. For example, the count operation detection unit 26 may output an enable signal indicating validity during a period in which the loop count unit 24 is performing a count operation and indicating invalidity during a period in which the loop count unit 24 is not performing a count operation. . As an example, the count operation detection unit 26 counts the loop count unit 24 when the loop count unit 24 performs an operation of reducing the count value by 1 every time it takes a set pulse number as a count value and receives a pulse from the loop circuit. When the value is other than 0, it may be detected that the loop count unit 24 is performing the counting operation.

  The end detection unit 28 determines whether or not the count operation in which the loop counting unit 24 counts the number of pulses circulating in the loop circuit by the number of set pulses is performed a predetermined number of times. As an example, the end detection unit 28 counts the number of times the enable signal output from the count operation detection unit 26 becomes valid, and determines whether the loop count unit 24 has performed the count operation for a predetermined number of times. You can judge. For example, the end detection unit 28 may output an end flag when the loop count unit 24 performs a count operation for a predetermined number of times.

  The reference clock count unit 30 counts a reference clock having a known cycle while the loop count unit 24 performs a counting operation for counting the number of pulses circulating in the loop circuit by a preset number of pulses. The reference clock count unit 30 holds the number of reference clocks as a count result. Thus, the reference clock count unit 30 can hold a value representing the time during which the loop count unit 24 is performing the counting operation. As an example, the reference clock count unit 30 may increase the number of reference clocks held by 1 each time a reference clock is received from the outside. For example, the reference clock count unit 30 may count the reference clock in a period in which the enable signal output from the count operation detection unit 26 is valid, and stop the count in a period in which the enable signal is invalid. .

  Further, the reference clock count unit 30 accumulates the number of reference clocks obtained each time the loop count unit 24 performs a count operation. That is, the reference clock count unit 30 counts the number of reference clocks accumulated plural times while the loop count unit 24 counts a predetermined number of set pulses. For example, the reference clock count unit 30 initializes the number of reference clocks to, for example, 0 at the start of the first count operation by the loop count unit 24, and starts the second and subsequent count operations by the loop count unit 24. The counting operation may be started from the number of reference clocks at the end of the previous counting operation. As an example, the reference clock count unit 30 may initialize the number of held reference clocks to 0, for example, in response to an external initialization signal.

  The control unit 32 controls the operation of the measurement apparatus 10. As an example, the control unit 32 may give an instruction to input a pulse to the loop circuit to the pulse input unit 22 at the start of the measurement operation. Further, as an example, the control unit 32 may supply a count operation start instruction to the loop count unit 24 a plurality of times, and cause the loop count unit 24 to perform a count operation a plurality of times.

  Further, as an example, the control unit 32 may supply an initialization signal instructing the initialization of the count value to the reference clock count unit 30 prior to each of the count operations started by the loop count unit 24. . Further, as an example, the control unit 32 prohibits initialization of the number of reference clocks counted by the reference clock count unit 30 at the start of the second and subsequent count operations by the loop count unit 24. A signal may be generated.

  The initialization prohibition unit 34 supplies an initialization signal, which is supplied to the reference clock count unit 30 prior to the start of a plurality of count operations by the loop count unit 24, to instruct the initialization of the count value. It is disabled at the start of the second and subsequent count operations by the unit 24. That is, at the start of the first count operation by the loop count unit 24, the initialization prohibiting unit 34 supplies an initialization signal to the reference clock count unit 30 and performs the second and subsequent count operations by the loop count unit 24. At the start, the supply of the initialization signal to the reference clock count unit 30 is prohibited. Accordingly, the initialization prohibition unit 34 can cause the reference clock count unit 30 to accumulate and hold the number of reference clocks for each count operation executed by the loop count unit 24 a plurality of times.

  For example, the initialization prohibition unit 34 may include an AND circuit 48. The AND circuit 48 receives an initialization signal from the control unit 32 that indicates validity when instructing initialization of the count value, and indicates invalidity when not instructing initialization of the count value. The AND circuit 48 receives an initialization prohibition signal indicating invalidity at the start of the first and subsequent count operations by the loop count unit 24 and indicating validity at the start of the second and subsequent count operations by the loop count unit 24. . Then, the AND circuit 48 provides the reference clock count unit 30 with a result obtained by performing an AND operation on the initialization signal and the inverted signal of the initialization inhibition signal. Thereby, the AND circuit 48 can disable the initialization signal supplied to the reference clock count unit 30 at the start of the second and subsequent count operations by the loop count unit 24.

  The offset storage unit 36 stores the number of reference clocks counted by the reference clock count unit 30 for a loop circuit that does not include the variable delay circuit 300. The subtracting unit 38 subtracts the number stored in the offset storage unit 36 from the number of reference clocks counted by the reference clock counting unit 30 for the loop circuit including the variable delay circuit 300. The selection unit 40 selects and outputs the reference clock number output from the reference clock count unit 30 or the subtraction unit 38.

  The memory unit 42 stores the reference clock number output by at least one of the reference clock count unit 30 and the subtraction unit 38 at different addresses for each of the plurality of delay setting values to be given to the variable delay circuit 300 to be measured. As an example, the memory unit 42 provides at least the reference clock count unit 30 and the subtraction unit 38 measured by applying the delay set value to the reference clock count unit 30 at an address on the memory unit 42 according to the delay set value. Stores the accumulated number of reference clocks output by one side.

  FIG. 4 shows a processing flow of the measuring apparatus 10. When the test apparatus 100 is calibrated, the measurement apparatus 10 performs the following steps S11 to S19 for each of the plurality of variable delay circuits 300 provided in the test apparatus 100.

  First, the loop connection unit 20 forms a loop circuit that does not include the variable delay circuit 300 (step S11). Subsequently, the measuring apparatus 10 causes the reference clock count unit 30 to accumulate and count the number of reference clocks while counting pulses set in the loop circuit not including the variable delay circuit 300 for the set number of pulses. A measurement process is executed (step S12). Details of the measurement process in step S12 will be described with reference to FIG. Subsequently, the control unit 32 acquires, from the reference clock count unit 30, a result of accumulating the number of reference clocks a predetermined number of times while counting the number of pulses that circulate in the loop circuit that does not include the variable delay circuit 300 for the set number of pulses. The data is written in the offset storage unit 36 (step S13).

  Subsequently, the loop connection unit 20 connects the output of the variable delay circuit 300 to be measured to the input of the variable delay circuit 300 to form a loop circuit including the variable delay circuit 300 and the loop connection unit 20 (step S14). ). Subsequently, the measuring apparatus 10 executes the processing from step S16 to step S18 for each of the plurality of delay setting values given to the variable delay circuit 300 to be measured (step S15, step S19).

  First, the setting unit 16 gives a delay setting value to the variable delay circuit 300 to be measured (step S16). As a result, the variable delay circuit 300 delays and outputs the input signal with a delay amount corresponding to the delay setting value.

  Subsequently, the control unit 32 causes the number of reference clocks to be accumulated and counted a predetermined number of times while the number of pulses circulating through the loop circuit including the variable delay circuit 300 and the loop connection unit 20 is counted. Is executed (step S17). Details of the measurement process in step S17 will be described with reference to FIG.

  Subsequently, the controller 32 accumulates the result of accumulating the number of reference clocks a predetermined number of times while counting the number of pulses that circulate through the loop circuit including the variable delay circuit 300 and the loop connection unit 20 as the delay setting value. The data is stored in the address on the memory unit 42 specified accordingly (step S18). Instead of this, or in addition to this, the control unit 32 determines the number of reference clocks for a predetermined number of times while counting the number of pulses circulating through the loop circuit including the variable delay circuit 300 and the loop connection unit 20. A result obtained by subtracting the number of reference clocks stored in the offset storage unit 36 from the accumulated result may be stored in the memory unit 42. Thus, the control unit 32 sets the delay time obtained by removing the delay time due to the loop connection unit 20 from the delay time of the loop circuit including the variable delay circuit 300 and the loop connection unit 20, that is, the delay time of only the variable delay circuit 300. The corresponding number of reference clocks can be stored in the memory unit 42.

  And if the process of step S16 to step S18 is complete | finished about each of several delay setting value, the measuring apparatus 10 will complete | finish a process. When the measurement of the delay time for each delay setting value of the variable delay circuit 300 by the measurement apparatus 10 is completed, the test apparatus 100 reads out the measurement result stored in the memory unit 42 and stores it in the linearization memory 310. Is generated.

  FIG. 5 shows a detailed flow of steps S12 and S17 of FIG. In step S12 and step S17 in FIG. 4, the control unit 32 repeats the following processing from step S32 to step S38 a predetermined number of times (step S31, step S39). Note that the predetermined number of times is a plurality of times.

  First, the pulse input unit 22 inputs one pulse into the loop circuit formed by the loop connection unit 20 (step S32). As a result, a pulse circulates in the loop circuit in the cycle of the delay time of the loop circuit.

  Subsequently, the control unit 32 determines whether the repetitive processing from step S32 to step S38 is the first time or after the second time (step S33). Subsequently, when the repetitive process is the first time (Yes in Step S33), the control unit 32 initializes the number of reference clocks held in the reference clock count unit 30 (Step S34). As an example, the control unit 32 may provide an initialization signal to the reference clock count unit 30 to initialize the number of reference clocks held in the reference clock count unit 30 to zero.

  When the repetitive processing from step S32 to step S38 is the second or later (No in step S33), the control unit 32 does not initialize the number of reference clocks held in the reference clock count unit 30 (that is, With the number of reference clocks held in the reference clock count unit 30 as it is), the process proceeds to the next step S35. For example, the control unit 32 may supply an initialization prohibition signal for prohibiting initialization to the initialization prohibition unit 34 to disable the initialization prohibition unit 34. As a result, the initialization prohibition unit 34 can prohibit the initialization of the number of reference clocks of the reference clock count unit 30 after the second iteration.

  Subsequently, the loop count unit 24 starts counting the number of pulses circulating in the loop circuit formed by the loop connection unit 20 (step S35). As an example, the loop count unit 24 captures a preset number of pulses as a count value in response to receiving a start signal given from the control unit 32, and captures it every time a pulse circulating in the loop circuit is received. The count value may be decreased by one.

  Furthermore, while the loop count unit 24 counts the number of pulses circulating in the loop circuit, the reference clock count unit 30 counts the number of reference clocks. Further, the reference clock count unit 30 increases the count value by 1 from the initial value (for example, 0) when the repetition processing from step S32 to step S38 is the first time. Further, when the repetitive process is performed for the second time or later, the reference clock count unit 30 increases the count value by 1 from the count value at the end of the previous repetitive process.

  Subsequently, the loop count unit 24 determines whether or not the count value of the number of pulses circulating in the loop circuit formed by the loop connection unit 20 has reached the set number of pulses (step S36). When the count value of the number of circulating pulses reaches the set number of pulses, the count is stopped (step S37). For example, the loop count unit 24 takes in the number of set pulses as a count value, and counts the count value when the count value becomes 0 if the count value is decreased by 1 every time a pulse is received from the loop circuit. You may stop.

  Further, the reference clock count unit 30 stops counting the number of reference clocks when the loop count unit 24 finishes counting the number of pulses circulating in the loop circuit. For example, if the count value is decreased by 1 each time the loop count unit 24 receives a pulse from the loop circuit, the reference clock count unit 30 determines that the reference clock count of the reference clock is 0. The number counting may be stopped.

  Subsequently, the control unit 32 causes the process to wait for a predetermined time (step S38). Subsequently, the control unit 32 determines whether or not the processing from step S32 to step S38 has been executed a predetermined number of times (step S39). If the process from step S32 to step S38 has not been executed a predetermined number of times, the process returns to step S32. If the process from step S32 to step S38 has been executed a predetermined number of times, the process proceeds to step S32. Proceed to S40.

  Subsequently, the control unit 32 outputs the number of reference clocks counted by the reference clock count unit 30 as a measurement result (step S40). When executing the process of step S <b> 12, the control unit 32 may output the number of reference clocks counted by the reference clock count unit 30 to the offset storage unit 36. Further, when executing the process of step S17, the control unit 32 may transfer the number of reference clocks counted by the reference clock count unit 30 to the memory unit 42, or the reference clock count unit 30 may count. The result of subtracting the number of reference clocks stored in the offset storage unit 36 from the number of reference clocks may be transferred to the memory unit 42.

  FIG. 6 shows an example of a variation in the delay time of the loop circuit formed by the loop connection unit 20, an example of the count number of the reference clock, and an example of the initialization prohibiting signal. The reference clock count unit 30 counts the number of reference clocks during a period in which the number of pulses circulating through the loop circuit formed by the loop connection unit 20 is counted for the set number of pulses.

  Here, the number of reference clocks counted by the reference clock counting unit 30 in this period is a value proportional to the delay time of the loop circuit formed by the loop connection unit 20 (that is, the number of pulses set in the delay time of the loop circuit). The value obtained by dividing the time multiplied by the period of the reference clock). Further, the period of the reference clock is known.

  Therefore, according to the measuring apparatus 10, by calculating a value obtained by dividing a value obtained by multiplying the number of reference clocks counted by the reference clock counting unit 30 in the period with the period of the reference clock by the number of set pulses, The delay time of the loop circuit formed by the connection unit 20 can be calculated. Furthermore, the measuring apparatus 10 can calculate the delay time of only the variable delay circuit 300 by subtracting the delay time of the loop circuit not including the variable delay circuit 300 from the delay time of the loop circuit including the variable delay circuit 300. it can.

  Further, the delay time of the loop circuit formed by the loop connection unit 20 varies depending on, for example, the power supply voltage and the ambient temperature, as shown in FIG. Here, as shown in FIG. 6B, the loop count unit 24 executes a counting process of counting the number of pulses circulating in the loop circuit by the set number of pulses a plurality of times at predetermined intervals. Then, the reference clock count unit 30 counts the number of reference clocks in each period of the plurality of count processes by the loop count unit 24. Thereby, it is possible to average the influence of the fluctuation of the delay time of the loop circuit. Therefore, according to the measuring apparatus 10, the delay time of the loop circuit formed by the loop connection unit 20 can be accurately measured regardless of the influence of fluctuations in the delay time of the loop circuit.

  Further, as shown in FIG. 6C, the reference clock count unit 30 accumulates the number of reference clocks in each period of the plurality of count processes by the loop count unit 24, and the last count by the loop count unit 24. After the processing, the number of reference clocks is read and output to the outside. For example, as shown in FIG. 6D, the reference clock count unit 30 initializes the number of reference clocks prior to the first count processing by the loop count unit 24, and the loop count unit 24 sets 2 In the count processing after the first time, an initialization prohibiting signal is given, and initialization of the number of reference clocks is prohibited. Therefore, according to the measuring apparatus 10, it is not necessary to read the number of reference clocks for each of a plurality of count processes by the loop count unit 24. Thereby, according to the measuring apparatus 10, the delay time of the loop circuit formed by the loop connection part 20 can be measured in a short time.

  FIG. 7 shows the configuration of the measuring apparatus 10 according to the first modification example of the present embodiment, together with the variable delay circuit 300. Note that the measurement apparatus 10 according to the present modification has substantially the same function and configuration as the measurement apparatus 10 shown in FIG. 3, and therefore members having substantially the same configuration and function as those shown in FIG. The same reference numerals are used, and the description is omitted except for the differences.

  The measurement apparatus 10 may further include a determination unit 50. The determination unit 50 determines whether or not the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 is within a preset target range. Further, in the present modification, the memory unit 42 receives a plurality of reference clock numbers output by at least one of the reference clock count unit 30 and the subtraction unit 38 and a determination result indicating whether or not the delay time is within the target range. Each delay setting value is stored in a different address.

  For example, when creating a table to be stored in the linearized memory 310, a delay setting value closer to the delay time specified by the delay specification value is selected from the actual delay time measurement results for each delay setting value. A process of searching and associating the delay designation value with the delay setting value is performed. Therefore, by setting a target range of the number of reference clocks according to the delay designation value in the determination unit 50 in advance, the measuring apparatus 10 according to the present modification can generate a signal corresponding to the delay time designated by the delay designation value. It is possible to determine whether or not the delay setting value can be delayed.

  FIG. 8 shows an example of the configuration of the determination unit 50 according to this modification. For example, the determination unit 50 may include an upper limit comparison unit 52 and a lower limit comparison unit 54.

  The upper limit comparison unit 52 compares the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 with an upper limit target value that represents a preset upper limit of the target range, and displays an upper limit comparison result that represents a comparison result. (For example, HFAIL in FIG. 8) is output. For example, the upper limit comparison unit 52 may output an upper limit comparison result indicating whether or not the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 is larger than the upper limit target value.

  The lower limit comparing unit 54 compares the number of reference clocks output from the reference clock counting unit 30 or the subtracting unit 38 with a lower limit target value that represents a preset lower limit of the target range, and a lower limit comparison result that represents a comparison result. (For example, LFAIL in FIG. 8) is output. As an example, the upper limit comparison unit 52 may output a lower limit comparison result indicating whether or not the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 is smaller than a lower limit target value. Such a determination unit 50 can determine whether or not the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 is within a preset target range.

  FIG. 9 shows an example of the configuration of the memory unit 42. For example, the memory unit 42 may include an address counter 62 and a memory circuit 64.

  The address counter 62 changes the address of the address counter 62 every time the end detection unit 28 outputs an end flag. In other words, the address counter 62 changes the address of the address counter 62 in response to the count operation in which the loop count unit 24 counts pulses for the set number of pulses for a predetermined number of times. For example, the address counter 62 may increment the address by one each time the end detection unit 28 outputs an end flag.

  The memory circuit 64 outputs the reference clock number output by at least one of the reference clock count unit 30 and the subtraction unit 38, the upper limit determination result (for example, HFAIL in FIG. 9) and the lower limit determination result (for example, FIG. 9) output by the determination unit 50. LFAIL) is received as write data. The memory circuit 64 stores the reference clock number and the determination result output by the determination unit 50 at the address specified by the address counter 62 at the timing when the end detection unit 28 outputs the end flag. Such a memory unit 42 sets the reference clock number output by at least one of the reference clock count unit 30 and the subtraction unit 38 and the determination result output by the determination unit 50 to different addresses for each of the plurality of delay setting values. Can be remembered.

  FIG. 10 shows an example of data written in the memory circuit 64 of FIG. For example, the memory circuit 64 may store 20-bit data at each address (for example, addresses 0 to 31 in FIG. 10).

  As an example, the memory circuit 64 may store the HFAIL flag in the 20th bit (bit [19] in FIG. 10) of the 20-bit data. For example, the HFAIL flag represents 1 when the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 is larger than the upper limit target value, and represents 0 when the number is less than the upper limit target value.

  For example, the memory circuit 64 may store the LFAIL flag in the 19th bit (bit [18] in FIG. 10) in 20-bit data. As an example, the LFAIL flag represents 1 when the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 is smaller than the lower limit target value, and represents 0 when the number is higher than the upper limit target value.

  Further, the memory circuit 64 sets the number of reference clocks output from the reference clock count unit 30 or the subtraction unit 38 from the first bit to the 18th bit (bits [17: 0] in FIG. 10) in the 20-bit data. You may remember. The memory circuit 64 configured as described above can store the determination result output from the determination unit 50 and the number of reference clocks for each delay setting value of the variable delay circuit 300.

  FIG. 11 shows an example of the configuration of the memory circuit 64 of FIG. As an example, memory circuit 64 includes an instruction decoder 70, a memory cell 72, an address decoder 74, a write / read gate 76, an HFAIL batch read gate 80, an LFAIL batch read gate 82, and an output unit 84. It's okay.

  In response to receiving a write command for writing data to an address corresponding to each of a plurality of delay setting values, the instruction decoder 70 supplies the address indicated by the write command to the address decoder 74 and write enable. Output a signal. In response to receiving a read command for reading data from an address corresponding to each of a plurality of delay setting values, the instruction decoder 70 supplies the address indicated by the read command to the address decoder 74 and a read enable. Output a signal.

  The instruction decoder 70 outputs an HFAIL read enable signal in response to receiving a plurality of upper limit determination result batch read commands corresponding to a plurality of delay setting values. The instruction decoder 70 outputs an LFAIL read enable signal in response to receiving a plurality of lower limit determination result batch read commands corresponding to a plurality of delay setting values.

  Memory cell 72 includes a plurality of cells storing data in bit units. The address decoder 74 specifies a cell to be written or read based on the address received from the instruction decoder 70.

  The write / read gate 76 (76-1, 76-2) receives data (ie, the number of reference clocks) supplied from the outside to the cell designated by the address decoder 74 in response to the output of the write enable signal. , Lower limit determination result and upper limit determination result) are stored. Also, the write / read gate 76 determines the number of reference clocks corresponding to the delay setting value to be read and the lower limit determination for the data stored in the cell designated by the address decoder 74 in response to the output of the read enable signal. The result and the upper limit judgment result are output.

  In response to the output of the HFAIL enable signal, the HFAIL batch read gate 80 reads data from a plurality of cells in which a plurality of upper limit determination results corresponding to a plurality of delay setting values are stored, Output as data including upper limit judgment result. For example, the HFAIL batch read gate 80 may collectively read and output data from the 20th bit cell of each address in the memory cell 72 in response to the output of the HFAIL enable signal.

  In response to the output of the LFAIL enable signal, the LFAIL batch read gate 82 collectively reads data from a plurality of cells storing a plurality of lower limit determination results corresponding to a plurality of delay setting values. Output as data including the lower limit judgment result. For example, the LFAIL batch read gate 82 may collectively read and output data from the 19th bit cell of each address in the memory cell 72 in response to the output of the LFAIL enable signal.

  The output unit 84 combines the data read from each address of the memory cell 72 through a separate data line with the data transmitted on the common data line and outputs the data to the outside. When the memory circuit 64 having such a configuration receives a batch read command of a plurality of determination results corresponding to a plurality of delay setting values, the memory circuit 64 may output data including a plurality of determination results corresponding to the plurality of delay setting values. it can. As a result, the memory circuit 64 can read only the determination result in advance, so that the number of accesses to the memory circuit 64 can be reduced. As a result, according to the memory circuit 64, the table stored in the linearized memory 310 can be created in a short time.

  FIG. 12 shows the configuration of the measuring apparatus 10 according to the second modification example of the present embodiment, together with the variable delay circuit 300. Note that the measurement apparatus 10 according to the present modification has substantially the same function and configuration as the measurement apparatus 10 shown in FIG. 3, and therefore members having substantially the same configuration and function as those shown in FIG. The same reference numerals are used, and the description is omitted except for the differences.

  The measurement apparatus 10 may further include a reference range determination unit 90. The reference range determination unit 90 determines whether or not the delay time of the variable delay circuit 300 based on the number of reference clocks output by at least one of the reference clock count unit 30 and the subtraction unit 38 is within a preset reference range. In this modification, the reference clock count unit 30 compares the delay time of the variable delay circuit 300 with the delay time determined to be within the reference range when the delay time of the variable delay circuit 300 is determined to be outside the reference range. Thus, the number of count operations may be reduced.

  For example, the reference range determination unit 90 may determine whether or not the number of reference clocks counted by the reference clock count unit 30 during the first counting operation by the loop count unit 24 is within the reference range. Then, when the reference range determination unit 90 determines that the number of reference clocks is within the reference range, the number of subsequent count operations by the loop count unit 24 is set to the first number, and the number of reference clocks is the reference number. If it is determined that it is out of the range, the number of subsequent count operations by the loop count unit 24 may be set to a second number smaller than the first number. Thereby, the reference range determination unit 90 determines the number of pulse count operations by the loop count unit 24 when there is a high possibility that the delay time of the variable delay circuit 300 corresponding to the delay setting value is greatly deviated from the target range. By reducing the time, the measurement time can be shortened.

  FIG. 13 shows the configuration of the measurement apparatus 10 according to the third modification example of the present embodiment, together with the variable delay circuit 300. Note that the measurement apparatus 10 according to the present modification has substantially the same function and configuration as the measurement apparatus 10 shown in FIG. 3, and therefore members having substantially the same configuration and function as those shown in FIG. The same reference numerals are used, and the description is omitted except for the differences.

  The reference clock counting unit 30 counts the reference clock by the number of set clocks when a set clock number that is a predetermined reference clock number is designated from the outside. For example, the reference clock count unit 30 may take the set clock number as a count value when an instruction to start a count operation is given, and decrease the count value by 1 each time a reference clock is received. The reference clock count unit 30 may stop the count operation when the count value reaches zero.

  Further, the reference clock count unit 30 repeats the count operation for counting the reference clocks by the number of set clocks a plurality of times. As an example, the reference clock count unit 30 may perform such a counting operation a plurality of times at predetermined intervals.

  The count operation detection unit 26 detects a period during which the reference clock count unit 30 performs a count operation for counting the reference clocks by the number of set clocks. For example, the count operation detection unit 26 outputs an enable signal indicating validity during a period during which the reference clock count unit 30 is performing a count operation and indicating invalidity during a period during which the reference clock count unit 30 is not performing a count operation. It's okay. The end detection unit 28 determines whether or not the reference clock counting unit 30 has performed the count operation for counting the reference clock by the set number of clocks a predetermined number of times.

  The loop count unit 24 counts pulses circulating in the loop circuit while the reference clock count unit 30 performs a count operation for counting the reference clocks by a preset number of clocks. Then, the loop count unit 24 holds the number of pulses as the count result. Thereby, the loop count unit 24 can hold a value representing the number of pulses circulating in the loop circuit during a predetermined time. For example, the loop count unit 24 may increase the number of held pulses by 1 each time a pulse is received from the loop circuit. Further, as an example, the loop count unit 24 counts pulses received from the loop circuit in a period in which the enable signal output from the count operation detection unit 26 is valid, and stops counting in a period in which the enable signal is invalid. You can do it.

  Furthermore, the loop count unit 24 accumulates the number of pulses obtained each time the reference clock count unit 30 executes the count operation. That is, the loop count unit 24 accumulates and counts the number of pulses circulating in the loop circuit while the reference clock count unit 30 counts a predetermined set number of clocks. For example, the loop count unit 24 initializes the number of pulses to, for example, 0 at the start of the first count operation by the reference clock count unit 30, and starts the second and subsequent count operations by the reference clock count unit 30. The counting operation may be started from the number of pulses at the end of the previous counting operation. As an example, the loop count unit 24 may initialize the number of held pulses to 0, for example, in response to an external initialization signal.

  The initialization prohibiting unit 34 supplies an initialization signal, which is supplied to the loop counting unit 24 prior to the start of a plurality of count operations by the reference clock counting unit 30, to instruct the initialization of the count value. It is disabled at the start of the second and subsequent counting operations by the counting unit 30. The offset storage unit 36 stores the number of pulses counted by the loop count unit 24 for a loop circuit that does not include the variable delay circuit 300.

  The subtracting unit 38 subtracts the number stored in the offset storage unit 36 from the number of pulses counted by the loop counting unit 24 for the loop circuit including the variable delay circuit 300. The selection unit 40 selects and outputs the number of pulses output from the loop count unit 24 or the subtraction unit 38. The memory unit 42 stores the number of pulses output by at least one of the loop count unit 24 and the subtracting unit 38 at different addresses for each of a plurality of delay setting values to be given to the variable delay circuit 300 to be measured.

  According to such a measuring apparatus 10 according to this modification, the same effects as those of the measuring apparatus 10 according to this embodiment shown in FIG. 3 can be obtained. That is, according to the measurement apparatus 10 according to the present modification, the loop connection is obtained by calculating a value obtained by dividing the value obtained by multiplying the set clock number by the period of the reference clock by the number of pulses counted by the loop count unit 24. The delay time of the loop circuit formed by the unit 20 can be calculated. Furthermore, the measuring apparatus 10 according to the present modification reduces the delay time of only the variable delay circuit 300 by subtracting the delay time of the loop circuit not including the variable delay circuit 300 from the delay time of the loop circuit including the variable delay circuit 300. Can be calculated.

  Further, according to the measuring apparatus 10 according to the present modification, the delay time of the loop circuit formed by the loop connection unit 20 can be accurately measured regardless of the influence of the fluctuation of the delay time of the loop circuit. Further, according to the measurement apparatus 10 according to the present modification, the number of pulses does not have to be read for each of the plurality of count processes by the reference clock count unit 30. Thereby, according to the measuring apparatus 10, the delay time of the loop circuit formed by the loop connection part 20 can be measured in a short time.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

FIG. 1 shows a configuration of a test apparatus 100 according to this embodiment together with a device under test 200. FIG. 2 shows the variable delay circuit 300 and the linearized memory 310 provided in the test apparatus 100 according to the present embodiment, and the measurement apparatus 10 that measures the delay time of the variable delay circuit 300. FIG. 3 shows the configuration of the measurement apparatus 10 according to the present embodiment, together with the variable delay circuit 300 that is the measurement target. FIG. 4 shows a processing flow of the measuring apparatus 10. FIG. 5 shows a detailed flow of steps S12 and S17 of FIG. FIG. 6 shows an example of a variation in the delay time of the loop circuit formed by the loop connection unit 20, an example of the count number of the reference clock, and an example of the initialization prohibiting signal. FIG. 7 shows the configuration of the measuring apparatus 10 according to the first modification example of the present embodiment, together with the variable delay circuit 300. FIG. 8 shows an example of the configuration of the determination unit 50 according to this modification. FIG. 9 shows an example of the configuration of the memory unit 42. FIG. 10 shows an example of data written in the memory circuit 64 of FIG. FIG. 11 shows an example of the configuration of the memory circuit 64 of FIG. FIG. 12 shows the configuration of the measuring apparatus 10 according to the second modification example of the present embodiment, together with the variable delay circuit 300. FIG. 13 shows the configuration of the measurement apparatus 10 according to the third modification example of the present embodiment, together with the variable delay circuit 300.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Measuring apparatus 16 Setting part 20 Loop connection part 22 Pulse input part 24 Loop count part 26 Count operation | movement detection part 28 End detection part 30 Reference | standard clock count part 32 Control part 34 Initialization prohibition part 36 Offset storage part 38 Subtraction part 40 Selection part 42 memory unit 44 pulse generation unit 46 OR circuit 48 AND circuit 50 determination unit 52 upper limit comparison unit 54 lower limit comparison unit 62 address counter 64 memory circuit 70 instruction decoder 72 memory cell 74 address decoder 76 write / read gate 80 HFAIL batch read gate 82 LFAIL batch readout gate 84 output unit 90 reference range determination unit 100 test device 122 pattern generation unit 124 timing generator 126 waveform shaping unit 128 driver 130 level comparator 132 timing comparator 134 determination unit 200 Device 300 variable delay circuits 310 linearization memory

Claims (10)

A measuring device for measuring a delay time of a delay circuit,
A loop connection for connecting the output of the delay circuit to the input of the delay circuit;
A loop count unit that counts pulses circulating in a loop circuit including the delay circuit and the loop connection unit;
A reference clock count unit for accumulating and counting the number of reference clocks while the loop count unit counts a predetermined number of pulses; and
A measuring apparatus comprising:   Prior to the start of a plurality of count operations, the initialization signal for instructing the initialization of the count value supplied to the reference clock count unit is disabled at the start of the second and subsequent count operations. The measurement apparatus according to claim 1, further comprising an initialization prohibition unit. A measuring device for measuring a delay time of a delay circuit,
A loop connection for selecting whether to form a loop circuit including the delay circuit by connecting an output of the delay circuit to an input of the delay circuit, or to form a loop circuit not including the delay circuit;
A pulse that circulates in the loop circuit that includes the delay circuit, and a loop count unit that counts pulses that circulate in the loop circuit that does not include the delay circuit;
For each of the loop circuit including the delay circuit and the loop circuit not including the delay circuit, a reference clock count unit that counts the number of reference clocks while the loop count unit counts a predetermined number of pulses;
An offset storage unit that stores the number of the reference clocks counted by the reference clock count unit for the loop circuit not including the delay circuit;
A subtractor for subtracting the number stored in the offset storage unit from the number of reference clocks counted by the reference clock count unit for the loop circuit including the delay circuit;
A measuring apparatus comprising:   The measurement apparatus according to claim 3, further comprising a determination unit that determines whether or not a reference clock number output from the reference clock count unit or the subtraction unit is within a preset target range. The delay circuit is a variable delay circuit that delays and outputs an input signal by a delay amount according to a given delay setting value,
The reference clock count unit counts the number of reference clocks while the loop count unit counts a predetermined number of pulses for each of the plurality of delay setting values,
5. The measurement according to claim 3, further comprising: a memory unit that stores, at different addresses, a reference clock number output by at least one of the reference clock count unit and the subtraction unit for each of the plurality of delay setting values. apparatus. The delay circuit is a variable delay circuit that delays and outputs an input signal by a delay amount according to a given delay setting value,
The reference clock count unit counts the number of reference clocks while the loop count unit counts a predetermined number of pulses for each of the plurality of delay setting values,
The measuring device is
A determination unit that determines whether the reference clock number output by the reference clock count unit or the subtraction unit is within a preset target range;
The reference clock number output by at least one of the reference clock count unit and the subtraction unit, and a determination result indicating whether or not the delay time is within the target range are set to different addresses for each of the plurality of delay setting values. The measuring apparatus according to claim 3, further comprising a memory unit for storing the data. The memory unit is
When a read command for an address corresponding to each of the plurality of delay setting values is received, the reference clock number corresponding to the delay setting value and the data stored in the address as the determination result are output,
The measurement apparatus according to claim 6, wherein when a batch read command of a plurality of determination results corresponding to the plurality of delay setting values is received, data including a plurality of determination results corresponding to the plurality of delay setting values is output. A reference range determination unit for determining whether a delay time of the delay circuit based on the reference clock number output from the reference clock count unit or the subtraction unit is within a preset reference range;
The reference clock count unit counts the number of count operations when the delay time of the delay circuit is determined to be out of the reference range, compared to the case where the delay time of the delay circuit is determined to be within the reference range. The measuring apparatus according to claim 3, wherein the measuring device is reduced. A measuring device for measuring a delay time of a delay circuit,
A loop connection for connecting the output of the delay circuit to the input of the delay circuit;
A reference clock count unit for counting the number of reference clocks;
A loop count that counts the number of pulses that circulate in the loop circuit including the delay circuit and the loop connection unit a plurality of times while the reference clock count unit counts a predetermined number of reference clocks. And
A measuring apparatus comprising: A test apparatus for testing a device under test,
A variable delay circuit that delays and outputs an input signal by a delay amount corresponding to a given delay setting value;
A measuring device for measuring the delay time of the variable delay circuit,
The measuring device is
A loop connection for connecting the output of the variable delay circuit to the input of the variable delay circuit;
A loop count unit for counting pulses circulating in a loop circuit including the variable delay circuit and the loop connection unit;
A reference clock count unit for accumulating and counting the number of reference clocks while the loop count unit counts a predetermined number of pulses; and
Test equipment with

Images