TWI490516B - Measuring device and method for automatic test equipment - Google Patents

Description

Measuring device and method for automatic test equipment

The present invention relates to a measuring device and method, and more particularly to a measuring device and method for an automatic testing device.

In the manufacturing process of all electronic devices, there is a need to de-storage. This need is actually a test process. Achieving this process requires a variety of test equipment, such as the so-called Automatic Test Equipment (ATE). In the field of automatic testing, how to shorten the test time has always been a very important issue, and the shortened test time represents the cost reduction of the product.

Please refer to FIG. 1, which is a circuit diagram of an automatic test equipment of the prior art. As shown in the figure, the conventional automatic test equipment includes a plurality of test channels CH1, CH2, ..., CHn-1, CHn, and the test channels CH1, CH2, ..., CHn-1, and CHn are connected to a Parametric Measurement Unit (Parametric Measurement Unit, PMU), and each test channel includes a Per Pin Parametric Measurement Unit (PPMU). The parameter measuring unit PMU is used to provide accurate four-quadrant measurement (VFIM, IFVM, VMM), but the disadvantage is that the number is small. Usually 64 test channels can only be assigned to one parameter measuring unit PMU, so that the parameter measuring unit PMU The plurality of pins to be tested, PIN1, PIN2, PINn-1, and PINn, are measured in turn, and thus it takes too much time. And the pin parameter measuring unit PPMU can separately measure the pin The pins CH1, CH2, ..., CHn-1, CHn are to be tested, but only the measured signal MS can be output to a comparator, and the comparison signal MS is passed/not passed (GO/NO- GO) measurement, that is to say, the pin parameter measuring unit PPMU can only be used to test whether the object to be tested in each test channel can be used, and cannot read the actual test value, so it is also less accurate. Therefore, the parameter measuring unit PMU and the pin parameter measuring unit PPMU each have advantages and disadvantages.

It can be seen from the above that the parameter measuring unit PMU can provide accurate four-quadrant measurement, but the number of parameter measuring units PMU is small and the measuring time is too long. The pin parameter measuring unit PPMU can measure each test channel at the same time. The measurement speed is fast, but only a rough measurement of pass/fail can be provided. Therefore, the use of conventional automatic test equipment does not achieve a precise and fast measurement method.

Furthermore, when the automatic test equipment measures the test channel, a host sends a measurement command through a bus to the automatic test equipment. When it is necessary to measure the plurality of test channels or to measure different components of the test object at the same time, The host must issue all shutdown commands before testing each test channel, and then issue an open command to open the test channel to be measured. Therefore, the more test channels or components are measured, the more measurement commands must be issued, so When the above software control method measures many test channels or components, there is a problem that the measurement speed is too slow, and the above method will occupy too much resources of the bus bar.

In addition, since the cost of the parameter measuring unit PMU is high, if the number of the parameter measuring unit PMU is increased, the cost of the overall automatic measuring device is increased.

Therefore, the present invention provides a method for selecting the plurality of pin measuring units in sequence by using the control unit, so that the pin parameter measuring units sequentially measure the plurality of measuring units. The measuring pin is used. Thus, the present invention utilizes the hardware circuit measurement of the control unit to achieve a measuring device and method for quickly measuring the automatic testing devices of the tested pins.

An object of the present invention is to provide a measuring device and method for an automatic testing device, which sequentially selects a plurality of pin parameter measuring units by a hardware circuit of a control unit, so that the pin parameter measuring units are The plurality of pins to be tested are sequentially measured to quickly measure the pins to be tested, thereby achieving the purpose of shortening the test time.

In order to achieve the above-mentioned various purposes and effects, the present invention discloses a measuring device for an automatic test device, which comprises a plurality of pin measuring units, an analog-to-digital converter and a control unit. Each of the pin parameter measuring units of the pin parameter measuring unit is configured to measure a pin to be tested to generate a measuring signal, and the analog digital converter is configured to convert the measuring signal into a reading signal. The control unit is electrically connected to the analog digital converter for selecting one of the pin parameter measuring units, and controls the analog digital converter to perform conversion to receive the reading signal. In this way, the present invention sequentially selects the pin parameter measuring units by the control unit, so that the pin parameter measuring units sequentially measure the plurality of pins to be tested to quickly measure the to-be-tested pins. In turn, the purpose of shortening the test time is achieved.

The invention further discloses a measuring method of an automatic testing device, which is applied to a plurality of pin parameter measuring units of a measuring device electrically connected to an automatic testing device, and the measuring method comprises: selecting the plurality according to a selection signal One of the pin parameter measuring units; driving the selected pin parameter measuring unit to measure one of the to-be-tested pins to generate a measuring signal; and outputting the selected pin parameter measuring unit The test signal is converted to a read signal.

10‧‧‧ analog digital converter

20‧‧‧Control unit

21‧‧‧Checklist unit

23‧‧‧Select control unit

25‧‧‧Correct memory circuit

251‧‧‧First forward and reverse

252‧‧‧Selector

253‧‧‧second flip-flop

254‧‧‧gain memory unit

255‧‧‧Compensated memory unit

256‧‧‧third positive and negative

257‧‧‧fourth flip-flop

27‧‧‧correction circuit

271‧‧‧Multiplier

273‧‧‧Adder

29‧‧‧Storage unit

40‧‧‧Host

60‧‧‧Selection unit

CH1‧‧‧ test channel

CH2‧‧‧ test channel

CHn-1‧‧‧ test channel

CHn‧‧ test channel

Gain‧‧‧ Gain parameters

MS‧‧‧Measurement signal

Offset‧‧‧compensation parameters

PIN1‧‧‧ pins to be tested

PIN2‧‧‧ pins to be tested

PINn-1‧‧‧ pins to be tested

PINn‧‧‧ pins to be tested

PMU‧‧‧Parameter Measurement Unit

PPMU‧‧‧ pin parameter measuring unit

R_add‧‧‧Read address

S_add‧‧‧ storage address

RWD‧‧‧Reading and writing signals

SP‧‧‧Select parameters

SS‧‧‧Select signal

VAL‧‧‧ reading signal

VAL’‧‧‧ actual reading signal

1 is a circuit diagram of an automatic test apparatus of the prior art; FIG. 2 is a circuit diagram of a measuring apparatus of an automatic test apparatus according to a first embodiment of the present invention; FIG. 3: BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a block diagram of a control unit of the present invention; FIG. 5 is a circuit diagram of a correction circuit of the present invention; Figure: is a block diagram of the calibration memory circuit of the present invention; Figure 7 is a schematic diagram of the measurement device of the automatic test equipment according to the second embodiment of the present invention; Figure 8 is a A flow chart of a measurement method of an automatic test device; and a figure 9 is a state diagram of a measurement method of the automatic test device of the present invention.

In order to provide a better understanding and understanding of the features and the efficacies of the present invention, the preferred embodiment and the detailed description are as follows: First, please refer to Figure 2, which is A circuit diagram of a measuring device of an automatic test apparatus according to a first embodiment of the present invention. As shown, the measuring device of the present invention comprises a plurality of pin parameter measuring units PPMU, an analog-to-digital converter 10 and a control unit 20. The pin parameter measuring units PPMU are respectively disposed on the plurality of test channels CH1, CH2, ..., CHn-1, CHn, and are respectively connected to the to-be-tested pins PINI, PIN2, ..., PINn-1, PINn of the object to be tested, and the measurement is performed. The pins PIN1, PIN2, ..., PINn-1, PINn are to be tested to generate a measurement signal MS, wherein the to-be-tested pins PIN1, PIN2... PINn-1 and PINn may be the pins of the same object to be tested or the pins of the plurality of objects to be tested. The analog digital converter 10 is connected to the output terminals of the pin parameter measuring units PPMU and is used to convert the measuring signal MS into a reading signal VAL. The control unit 20 is electrically connected to the analog-to-digital converter 10, and transmits a selection signal SS to the pin parameter measuring units PPMU to select one of the pin parameter measuring units PPMU to select the pin. The parameter measuring unit PPMU measures the corresponding pins to be tested (PIN1, PIN2...PINn-1, PINn), and analog signal converter 10 is connected to the pin parameter measuring unit PPMU. Converted to read value signal VAL.

Based on the above, the present invention utilizes the hardware circuits of the control unit 20 to sequentially select the pin parameter measuring units PPMU, so that the pin parameter measuring units PPMU sequentially measure the test channels CH1, CH2... The test pins of CHn-1 and CHn are used to quickly measure the test objects of the test channels CH1, CH2, ..., CHn-1 and CHn, thereby achieving the purpose of shortening the test time.

Generally, there is a bus BUS between the measuring device Tester and the host 40 as a communication transmission between the two. However, the communication time of the bus BUS varies with the load of the CPU of the host processor 40, so if the software is used, Measurements may further affect the measurement results. Moreover, since it is impossible to determine the hardware device of the terminal to be tested, the best method is to completely control the entire measurement program by the hardware circuit itself of the control unit 20, and can ensure that the measurement result is not affected by the host 40 bus BUS communication. The speed of time affects.

In addition, another advantage of the hardware circuit control measurement program of the present invention using the control unit 20 is that it does not occupy the resources of the host 40. During the measurement by the analog digital converter 10, the software can still pass through the host 40 and the bus BUS simultaneously. Setting other components, such as accessing memory or detecting temperature or voltage, can shorten the test Try and set the time.

In addition, the control unit 20 can further correct the read signal VAL to generate an actual read signal VAL' for reading by a host 40.

Please refer to FIG. 3, which is a schematic diagram of a measuring device of an automatic testing device according to a first embodiment of the present invention. As shown, the analog-to-digital converter 10 of the present invention can simultaneously connect any number of pin parameter measurement units PPMU. The control unit 20 is connected to the pin parameter measuring unit PPMU, and outputs a selection signal SS to the selected pin parameter measuring unit PPMU for the selected pin parameter measuring unit PPMU to measure correspondingly. A measurement signal MS is generated by measuring the pins (one of PIN1, PIN2, ..., PINn-1, PINn), and the measurement signal MS is transmitted to the analog-to-digital converter 10 for conversion.

Taking 64 test channels as an example, an analog-to-digital converter is responsible for measuring 16 test channels. The first analog-to-digital converter is responsible for testing channels CH1-CH16, and the second analog-to-digital converter is responsible for testing channels CH17-CH32. The third analog-to-digital converter is responsible for testing the channel CH33-CH48, the fourth analog-to-digital converter is responsible for testing the channel CH49-CH64, and the control unit corresponding to the first analog-to-digital converter is set to the measurement test channel CH1, 3, 5. The control unit corresponding to the second analog digital converter is set to the measurement test channel CH19, 25, 27. The control unit corresponding to the third analog digital converter is set to the measurement test channel CH35, 40, 44, and fourth. When the control unit corresponding to the analog-to-digital converter is set to measure the test channels CH49, 52, 64, the first analog-time digital converter measures the test channel CH1 and the second analog-digital converter at the first measurement time. Test channel CH19, the third analog converter measures the test channel CH35, the fourth analog converter measures the test channel CH49, and the second and third measurements time and so on

As can be seen from the above, the above architecture can simultaneously measure 4 test channels to increase the speed of automatic test equipment measurement. However, the present invention is not limited to the above-described number of test channels or the number of analog-to-digital converters. For example, a plurality of test channels can be measured by 1 to n analog-bit converters, where n is the total number of test channels.

Please refer to FIG. 4, which is a block diagram of the control unit of the present invention. As shown, the control unit 20 includes a look-up table unit 21, a selection control unit 23, a correction memory circuit 25, and a correction circuit 27. The lookup table unit 21 stores a plurality of selection parameters SP corresponding to the pin parameter measurement units PPMU. The selection control unit 23 is electrically connected to the look-up table unit 21, and generates a selection signal SS according to the selection parameters SP. The selection signal SS is used to select one of the pin parameter measurement units PPMU, and the selected one is selected. The foot parameter measuring unit PPMU measures the corresponding pin to be tested (one of PIN1, PIN2...PINn-1, PINn), and the selection signal SS can be regarded as a consistent energy signal for enabling the selected pin parameter measurement. Unit PPMU.

The correction memory circuit 25 is electrically connected to the look-up table unit 21 and is configured to store a complex gain parameter Gain and a complex compensation parameter Offset. The gain parameters Gain and the compensation parameters Offset correspond to the selection parameters SP, that is, each The test channel includes a complex measurement range, and each measurement range has a gain parameter Gain and a compensation parameter Offse, wherein the number of measurement ranges is determined by the specification of the pin parameter measurement unit PPMU.

The lookup unit 21 generates a read address R_add according to the read/write signal RWD of the host 40, and the read address R_add corresponds to the pin parameter measurement unit PPMU selected by the selection signal SS, and the correction memory circuit 25 reads according to The address R_add outputs a gain parameter Gain corresponding to the selected pin parameter measuring unit PPMU and a compensation parameter Offset. The correction circuit 27 is electrically connected to the correction memory circuit 25 and the analog digital converter 10, and The correction circuit 27 corrects the read signal VAL using the gain parameter Gain output from the correction memory circuit 25 and the compensation parameter Offset, and outputs the corrected actual read signal VAL' to the host 40.

For example, when the lookup unit 21 stores the selection parameters SP of the pin parameter measurement units PPMU corresponding to the test channels CH1, CH10 and CH16, the selection control unit 23 sequentially transmits the corresponding test channel CH1 according to the selection parameters SP. , the selection signal SS of the pin parameter measuring unit PPMU of CH10 and CH16, so that the pin parameter measuring unit PPMU sequentially measures the pins PIN1, PIN10 and PIN16 to be tested, respectively, when the amount of the test channel CH1 When the measuring unit PPMU measures the pin PIN1 to be tested and generates the reading signal VAL, the correction memory circuit 25 outputs the gain parameter Gain and the compensation parameter Offset corresponding to the test channel CH1 to the correction circuit 27 according to the reading address R_add at this time, so that the correction memory circuit 25 The correction circuit 27 uses the gain parameter Gain and the compensation parameter Offset to correct the read signal VAL at this time, and then sequentially performs the measurement of the test channels CH10 and CH16, and the measurement method is pushed in this way, and will not be described again.

In addition, in this embodiment, the control unit 20 further includes a storage unit 29 for receiving and storing the corrected actual read signal VAL' for reading by the host 40.

In addition, if the gain parameter Gain and the compensation parameter Offset are stored in the correction memory circuit 25 before the measurement, the correction memory circuit 25 determines that the memory state is stored according to the read/write signal RWD, so the correction memory circuit 25 according to a storage address S_add At this time, the gain parameter Gain transmitted from the host 40 and the compensation parameter Offset are stored to the corresponding address. The storage address S_add is generated by the host 40. For example, when the host 40 transmits the read/write signal RWD in the storage state to the lookup unit 21 and the correction memory circuit 25, and the host 40 also sequentially transmits the storage address S_add corresponding to the test channels CH1, CH10 and CH16 to the correction memory circuit 25, , the correction memory circuit 25 according to the corresponding storage state The read/write signal RWD is changed to the storage state, and when the storage address S_add corresponding to the test channel CH1 is transmitted to the correction memory circuit 25, the correction memory circuit 25 stores the gain parameter Gain and the compensation parameter Offset transmitted from the host 40 at this time. The storage address S_add corresponding to the test channel CH1 is followed by the storage operation of the test channels CH10 and CH16, and the rest are pushed in this way, and will not be described again.

Please refer to FIG. 5, which is a circuit diagram of the correction circuit of the present invention. As shown, the correction circuit 27 includes a multiplier 271 and an adder 273. The multiplier 271 is electrically connected to the analog-to-digital converter 10 and the correction memory circuit 25, receives the gain parameter Gain and the read value signal VAL, and multiplies the gain parameter Gain and the read value signal VAL to output. The adder 273 is electrically connected to the output end of the multiplier 271, receives the compensation parameter Offset and the multiplied read value signal VAL, and performs an addition operation to generate an actual read value signal VAL'.

Please refer to FIG. 6, which is a block diagram of the correction memory circuit of the present invention. As shown, the correction memory circuit 25 includes a first flip-flop 251, a selector 252, a second flip-flop 253, a gain memory unit 254, a compensation memory unit 255, and a third flip-flop 256. And a fourth flip-flop 257. The first flip-flop 251 is electrically connected to the look-up table unit 21, and obtains the read address R_add according to the read/write signal RWD and outputs it. The selector 252 can be a multiplexer electrically connected to the first flip-flop 251, and according to the read/write signal RWD, it is known that the write mode or the read mode is at this time, and a storage address S_add or read is selected. Take one of the addresses R_add output. The second flip-flop 253 is electrically connected to the selector 252, and obtains the output address S_add or the read address R_add output by the selector 252 and outputs it.

The gain memory unit 254 is electrically connected to the second flip-flop 253 for storing or reading the gain parameters Gain, that is, the gain memory unit 254 is received according to The storage address S_add is stored, and the gain parameter Gain outputted by the host 40 is stored in the address of the corresponding storage address S_add in the gain memory unit 254, or is output and stored in the gain memory unit 254 according to the received read address R_add. The gain parameter Gain corresponding to the address of the read address R_add. The compensation memory unit 255 is electrically connected to the second flip-flop 253 for storing or reading the compensation parameters Offset. That is, the compensation memory unit 255 outputs the host 40 according to the received storage address S_add. The compensation parameter Offset is stored in the address of the corresponding storage address S_add in the compensation memory unit 255, or the compensation stored in the address of the corresponding read address R_add in the compensation memory unit 255 is output according to the received read address R_add. The parameter Offset.

The third flip-flop 256 is electrically connected to the gain memory unit 254, and outputs the received gain parameter Gain to the multiplier 271 according to the read/write signal RWD. The fourth flip-flop 257 is electrically connected to the compensation memory unit 255, and outputs the received compensation parameter Offset to the adder 273 according to the read/write signal RWD. The read and write signal RWD may be generated by the lookup unit 21 or the host 40.

Please refer to FIG. 7, which is a schematic diagram of a measuring device of an automatic testing device according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the pin parameter measuring unit PPMU of the embodiment is connected to the analog-to-digital converter 10 through a selection unit 60, and the rest is not described again, and the detailed description thereof is as follows. .

As shown, the pin parameter measuring units PPMU are electrically connected to the plurality of input terminals of the selecting unit 60, and one of the selecting units 60 is electrically connected to the analog digital converter 10, and one of the selecting units 60 is controlled. The terminal is electrically connected to the control unit 20, and is configured to select one of the pin parameter measuring units PPMU according to the selection signal SS output by the control unit 20 to output the measuring signal MS to the analog digital converter 10, that is, The control unit 20 sends a selection signal SS to the selection unit 60 to control the selection unit 60. The pin parameter measuring unit PPMU is sequentially selected to measure the corresponding pin to be tested (one of PIN1, PIN2...PINn-1, PINn), that is, the pin to be tested PIN1, the pin to be tested PIN2 are sequentially selected... The pin PINn-1 to be tested and the pin PINn to be tested are sequentially converted by transmitting the measurement signal MS to the analog digital converter 10. The selection unit 60 of the embodiment may be a multiplexer.

Please refer to FIG. 8 together, which is a flowchart of the measuring method of the automatic test equipment of the present invention. The measuring method of the automatic testing device of the present invention is applied to a measuring circuit, and the measuring circuit is connected to the pin parameter measuring unit PPMU, and the measuring circuit comprises an analog digital converter 10 and a control unit 20. The measuring method of the present invention first performs step S10, and stores the complex gain parameter Gain and the complex compensation parameter Offset in the correction memory circuit 25, the gain parameters Gain and the compensation parameters Offset. Then, the step S20 is executed to store the plurality of selection parameters SP in the table lookup unit 21, the selection parameters SP are corresponding to the pin parameter measurement units PPMU, and the selection control unit 12 sequentially generates the plurality of selection signals SS according to the selection parameters SP. .

Then, step S30 is executed, and the pin parameter measuring units PPMU are sequentially selected according to the selection signals SS. Then, step S40 is executed to drive the selected pin parameter measuring unit PPMU to measure one of the to-be-tested pins (one of PIN1...PINn) to generate a corresponding measurement signal MS. Next, in step S50, the analog-to-digital converter 10 converts the measured signal MS output by the selected pin parameter measuring unit PPMU into a read signal VAL.

Then, in step S60, according to the read/write signal RWD, the lookup unit 21 generates a read address R_add, the read address R_add corresponds to the selected pin parameter measurement unit PPMU, and the correction memory circuit 25 outputs according to the read address R_add. Corresponding to the gain parameter Gain and the compensation parameter Offset of the selected pin parameter measuring unit PPMU. Then execute the step In step S70, the correction circuit 27 corrects the read value signal VAL generated in step S50 using the selected gain parameter Gain and the compensation parameter Offset to generate the actual read value signal VAL' for reading by the host 40.

In step S70, the correction circuit 27 multiplies the read value signal VAL by the selected gain parameter Gain, and then adds the selected compensation parameter Offset to generate the actual read value signal VAL'. In addition, in step S70, the read address R_add is outputted from the host 40 and the read address R_add is outputted to the selector 252, and the selector 252 is selected to select the storage address S_add or the read address R_add according to the read/write signal RWD. Then, the storage address S_add or the read address R_add is obtained and output to the correction memory circuit 25, so that the correction memory circuit 25 writes the gain parameter Gain, the compensation parameter Offset according to the storage address S_add, or drives the correction according to the read address R_add. The memory circuit 25 outputs the selected gain parameter Gain and the compensation parameter Offset.

Please refer to FIG. 9 together, which is a state diagram of the measuring method of the automatic test equipment of the present invention. This state diagram shows the state of the control unit 20. As shown, the control unit 20 is in the idle state ST10 before the measurement, and when the control unit 20 receives one of the trigger signals transmitted from the host 40, it is switched to the check state ST20. When the state ST20 is checked, the control unit 20 checks the test channels CH1-CHn according to the look-up table unit 21, and determines which test channel CH1-CHn is to be measured at this time, and converts to the set state ST30 after the check is completed.

When the state ST30 is set, the control unit 20 transmits the selection signal SS to the pin parameter measuring unit PPMU corresponding to the test channel (one of CH1-CHn) to be measured at this time, or transmits the corresponding measurement to be measured at this time. The selection signal SS of the test channel (one of CH1-CHn) is connected to the selection unit 60 to connect the analog digital converter 10 with the correct pin parameter amount. The measurement unit PPMU is converted to the steady state ST40 after the setting is completed. The steady state ST40 is used to delay a period of time to stabilize the setting made in the set state ST30.

Then, the control unit 20 transmits a read signal to the analog-to-digital converter 10, so that the analog-to-digital converter 10 starts reading the value of the measurement signal MS and converts it into a read signal. VAL, converted to the correction state ST60 after the reading is completed. In the correction state ST60, the control unit 20 corrects the read value signal VAL by the gain parameter Gain and the compensation parameter Offset, and outputs the result to the determination state ST70 after the correction is completed. When determining the state ST70, the control unit 20 determines whether the measurement of all the test channels CH1-CHn has been completed, and if it is completed, switches back to the idle state ST10, and if not, converts to the check state ST20, and the control unit 20 continues. Check the test channels CH1-CHn to determine the test channel (one of CH1-CHn) to be measured at this time.

In summary, the measuring device and method of the automatic test equipment of the present invention output an output of the pin parameter measuring unit by connecting an analog-type digital converter to the output end of the plurality of pin parameter measuring units. The measuring signal is converted into a reading signal, and one of the pin parameter measuring units to be measured is sequentially selected by a control unit to achieve the purpose of measuring the plurality of pins to be tested quickly and accurately.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

The invention is a novel, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China. With the application of the application, the praying office will grant the patent as soon as possible.

10‧‧‧ analog digital converter

20‧‧‧Control unit

40‧‧‧Host

CH1‧‧‧ test channel

CH2‧‧‧ test channel

CHn-1‧‧‧ test channel

CHn‧‧ test channel

MS‧‧‧Measurement signal

PIN1‧‧‧ pins to be tested

PIN2‧‧‧ pins to be tested

PINn-1‧‧‧ pins to be tested

PINn‧‧‧ pins to be tested

PPMU‧‧‧ pin parameter measuring unit

RWD‧‧‧Reading and writing signals

SS‧‧‧Select signal

VAL‧‧‧ reading signal

VAL’‧‧‧ actual reading signal

Claims (8)

A measuring device for an automatic testing device, comprising: a plurality of pin parameter measuring units, each pin parameter measuring unit for measuring a pin to be tested to generate a measuring signal; an analog to digital converter The control unit is configured to convert the measurement signal into a read value signal; a control unit is electrically connected to the analog digital converter for selecting one of the pin parameter measurement units, and controlling the analog digital converter Converting to receive the read signal; and a multiplexer having a control terminal, an output terminal, and a plurality of input terminals, wherein the control terminal is electrically connected to the control unit, and the output terminal is electrically connected to the analog digital converter. The input terminals are respectively electrically connected to the pin parameter measuring units, and are controlled by the control unit to select one of the pin parameter measuring units to output the measuring signal to the analog digital conversion Device. The measuring device of claim 1, wherein the control unit comprises: a look-up table unit for storing a plurality of selection parameters, the selection parameters corresponding to the pin parameter measuring units; and a selection control unit Electrically connected to the look-up unit for generating a selection signal for selecting one of the pin parameter measuring units according to the selection parameters; a correction memory circuit electrically connected to the table look-up unit The plurality of gain parameters and the plurality of compensation parameters are stored, and the gain parameters and the compensation parameters correspond to the selection parameters, and the look-up unit generates a read address according to a read/write signal, and the read address corresponds to the selected one. The pin parameter measuring unit, the correcting memory circuit is based on the reading Transmitting the gain parameter and the compensation parameter; and a correction circuit electrically connected to the correction memory circuit and the analog-to-digital converter, and correcting the read value by using the gain parameter output by the correction memory circuit and the compensation parameter Signal. The measuring device of claim 2, wherein the correction circuit comprises: a multiplier electrically connected to the analog-to-digital converter and the correction memory circuit for using the gain parameter and the read signal Performing a multiplication operation; and an adder electrically coupled to the multiplier for adding the output of the multiplier to the compensation parameter. The measurement device of claim 3, wherein the correction memory circuit further comprises: a first flip-flop device electrically connected to the look-up table unit for obtaining and outputting the read according to the read/write signal Taking a address; a selector electrically connected to the first flip-flop for selecting a storage address or the read address output according to the read/write signal; a second flip-flop electrically connected The selector is configured to obtain the storage address or the read address of the selector output, and output the storage address or the read address to a gain memory unit and a compensation memory unit to write or Reading the gain parameter or the compensation parameter; a third flip-flop is electrically connected to the gain memory unit for outputting the corresponding gain parameter to the multiplier according to the read/write signal; and a fourth positive and negative The device is electrically connected to the compensation memory unit for outputting the corresponding compensation parameter to the adder according to the read/write signal. The measuring device of claim 3, wherein the control unit further comprises: a storage unit is configured to store the read signal corrected by the multiplier and the adder for reading by a host. A measuring method for an automatic testing device, the measuring method is applied to a measuring circuit, the measuring circuit is electrically connected to the plurality of pin parameter measuring units of the automatic testing device, and the step of the measuring method comprises: Selecting a signal to select one of the pin parameter measuring units; driving the selected pin parameter measuring unit to measure one of the to-be-tested pins to generate a measuring signal; and selecting the pin The measurement signal outputted by the parameter measurement unit is converted into a read value signal; the plurality of selection parameters are stored in a lookup table unit, and the selection parameters correspond to the plurality of pin parameter measurement units to generate the selection according to the selection parameters. And storing the complex gain parameter and the complex compensation parameter in a correction memory circuit, wherein the gain parameters and the compensation parameters correspond to the selection parameters; according to a read/write signal, the lookup unit generates a read address, the read Taking the address corresponding to the selected pin parameter measuring unit, the correcting memory circuit outputs the gain parameter and the compensation parameter according to the read address; and using the selected one Compensation parameter correction parameter and the value of the read signal. The measuring method of claim 6, wherein the step of correcting the read signal by using the selected gain parameter and the compensation parameter comprises: multiplying the gain parameter and the read signal Computing; and adding the compensation parameter to the read signal after performing the multiplication operation. The measuring method of claim 6, wherein the step of correcting the read signal by using the selected gain parameter and the compensation parameter comprises: obtaining and outputting the reading according to the read/write signal Address to a selector; Driving the selector to select a storage address or the read address output according to the read/write signal; and obtaining the storage address or the read address of the selector output, and outputting the storage address or the reading Addressing the correction memory circuit for writing the gain parameter and the compensation parameter according to the storage address to the correction memory circuit or driving the correction memory circuit to select the gain parameter and the compensation according to the read address parameter.