CN117347818A - Delay measurement method, delay measurement device, delay measurement system and interface circuit - Google Patents

Abstract

The application discloses a delay line delay measurement method, a delay line delay measurement device, a delay line delay measurement system and an interface circuit, wherein the delay line delay measurement method comprises the following steps: and acquiring a measurement mode of the delay line and a bit width of a delay control signal of the delay line, wherein the measurement mode is used for showing a target measurement time of the delay line, determining a pre-delay stage number of the delay control signal for controlling the delay line to realize delay according to the bit width, judging the coincidence of a delay output result under the action of the delay control signal corresponding to the pre-delay stage number and the target measurement time, and adjusting the pre-delay stage number of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay stage number coincides with the target measurement time, so as to obtain the delay stage number corresponding to the target measurement time. Thus, the measurement can be flexibly performed for different measurement modes, and the number of measurement turns is remarkably reduced.

Description

Delay measurement method, delay measurement device, delay measurement system and interface circuit

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a delay measurement method, device, system, and interface circuit.

Background

Delay lines are widely used in various interface circuits, such as: the SOC (system On Chip) Chip needs to delay the DQS (Data strobe signal, data strobe) signal by 1/4 clock cycle with a delay line (delay) when reading Data in DDR (Double Data Rate) memory. The delay time of the delay line and dly_code (a group of multi-bit signals) have linear positive correlation, and the delay time of the delay line is increased by one delay unit (Dly _element) every 1 increment of dly_code. The step delay time of the delay line is the delay of one delay cell (Dly _element).

The delay time of the delay unit is related to the ambient temperature, voltage, etc. In the chip initialization stage, the delay time of the delay line equivalent to the target clock period is required to be measured, and the dly_code value corresponding to the equivalent delay time is recorded, so that different dly_code values are set for the delay line, and the expected delay time is set. For example, if the dly_code value corresponding to the equivalent delay time of one clock cycle is measured to be 100, the dly_code value corresponding to 1/4 clock cycle is 25.

Therefore, the target delay time cannot be accurately generated until the delay line delay time measurement is completed, so the delay measurement should be completed first before the delay is performed using the delay line, and the shorter the delay measurement time, the better. Meanwhile, the higher the accuracy of the delay time measurement is, the better.

The scheme mainly adopted at present is to reference a clock after clock sampling delay, and measure the clock by using a half period fixedly, but if the duty ratio of the clock to be measured is not exactly 50%, the error of the measurement result is increased. And the measurement period dly_code needs to be increased stepwise, the measurement time is long.

Disclosure of Invention

The embodiment of the application provides a delay measurement method, a delay measurement device, a delay measurement system and an interface circuit.

According to a first aspect of the present application, there is provided a delay measurement method of a delay line, the method comprising: acquiring a measurement mode of the delay line and a bit width of a delay control signal of the delay line, wherein the measurement mode is used for showing a target measurement time of the delay line; determining a pre-delay stage number of a delay control signal for controlling the delay line to realize delay according to the bit width; judging the coincidence of a delay output result under the action of a delay control signal corresponding to the pre-delay stage number and the target measurement time; and adjusting the pre-delay progression of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay progression coincides with the target measurement time, so as to obtain the delay progression corresponding to the target measurement time.

According to an embodiment of the present application, determining a pre-delay stage number of a delay control signal for controlling the delay line to implement delay according to the bit width includes: and taking the median of the delay control signal as the pre-delay stage number according to the bit width.

According to an embodiment of the present application, the taking the median of the delay control signal as the pre-delay stage number includes: and setting the highest position of the delay control signal to be 1 and setting the other positions to be zero.

According to an embodiment of the present application, the delay output result is used for showing an actual delay time under the action of the delay control signal corresponding to the delay progression; correspondingly, the judging the coincidence of the delay output result under the action of the delay control signal corresponding to the delay progression and the target measurement time includes: judging the magnitude relation between the actual delay time and the target measurement time; under the condition that the magnitude relation obtained by two adjacent delay series is opposite, judging that the delay output result is consistent with the target measurement time, and determining that the delay series of the delay control signal corresponding to one test with smaller delay difference in the two adjacent tests is the delay series corresponding to the target measurement time; wherein the delay difference is the difference between the actual delay time and the target measurement time.

According to an embodiment of the present application, the delay output result is used for showing an actual delay time under the action of the delay control signal corresponding to the delay progression; correspondingly, the adjusting the pre-delay stage number of the delay control signal according to the compliance includes: and when the actual delay time is greater than the target measurement time, adopting a dichotomy to adjust the pre-delay progression until the magnitude relation between the actual delay time and the target measurement time obtained by two adjacent delay progression is opposite.

According to an embodiment of the present application, the adjusting the pre-delay stage by using a dichotomy includes: when the actual delay time is greater than the target measurement time, setting the position with 1 in the previous pre-delay stage number as zero, and keeping other bits unchanged; and when the actual delay time is smaller than the target measurement time, the bit with the previous pre-delay stage number set to 1 is kept unchanged.

According to a second aspect of the present application, there is also provided a delay measurement apparatus for a delay line, the apparatus comprising: an acquisition module for acquiring a measurement mode of the delay line and a bit width of a delay control signal of the delay line, the measurement mode being used for showing a target measurement time of the delay line; the determining module is used for determining the pre-delay series of the delay control signal for controlling the delay line to realize delay according to the bit width; the judging module is used for judging the coincidence between the delay output result under the action of the delay control signal corresponding to the pre-delay stage number and the target measurement time; and the adjusting module is used for adjusting the pre-delay progression of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay progression coincides with the target measurement time, so as to obtain the delay progression corresponding to the target measurement time.

According to a third aspect of the present application, there is also provided a delay measurement system of a delay line, the system comprising: the file registering unit is used for receiving and storing a control file and a state file for measuring the delay of the delay line; the delay detection circuit unit is used for carrying out delay detection on the delay line based on the state file under the triggering of the measurement control unit and sending a delay output result; and the measurement control unit is used for acquiring the control file from the file registering unit, triggering the delay detection circuit unit to carry out delay detection, acquiring the delay output result from the delay detection circuit unit, and updating the state file according to the delay output result.

According to an embodiment of the present application, the state file includes a measurement mode subfile for showing a target measurement time of the delay line and a bit width subfile for showing a bit width of a delay control signal; correspondingly, the measurement control unit updates the state file according to the delayed output result, and the measurement control unit comprises: determining a pre-delay stage number of a delay control signal for controlling the delay line to realize delay according to the bit width; judging the coincidence of a delay output result under the action of a delay control signal corresponding to the pre-delay stage number and the target measurement time; and adjusting the pre-delay progression of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay progression coincides with the target measurement time, so as to obtain the delay progression corresponding to the target measurement time.

According to a fourth aspect of the present application there is also provided an interface circuit for which delay measurements are required, the interface circuit comprising the delay measurement system described above.

According to the delay measurement method of the delay line, a measurement mode of the delay line and the bit width of a delay control signal of the delay line are obtained, the measurement mode is used for showing target measurement time of the delay line, a pre-delay stage number of the delay control signal for controlling the delay line to realize delay is determined according to the bit width, the coincidence of a delay output result under the action of the delay control signal corresponding to the pre-delay stage number and the target measurement time is judged, the pre-delay stage number of the delay control signal is adjusted according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay stage number coincides with the target measurement time, and the delay stage number corresponding to the target measurement time is obtained. In this way, the measurement can be flexibly performed for different measurement modes, for example: the measurement can be performed in 0.25T, 0.5T or 1T modes respectively, wherein the measurement mode is not influenced by the clock duty ratio when being the 1T mode, and the measurement result is more accurate. Further, the number of pre-delay stages of the delay control signal for delaying the delay line is determined and controlled according to the bit width, and the number of pre-delay stages of the delay control signal is adjusted according to the coincidence between the delay output result under the action of the delay control signal corresponding to the number of pre-delay stages and the target measurement time, so that the number of measurement turns can be remarkably reduced.

It should be understood that the teachings of the present application are not required to achieve all of the above-described benefits, but rather that certain technical solutions may achieve certain technical effects, and that other embodiments of the present application may also achieve benefits not mentioned above.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

Fig. 1 is a schematic diagram of an application scenario of a delay measurement method of a delay line according to an embodiment of the present application;

FIG. 2 shows a timing diagram of the register sample setup and hold times of a DDR memory;

FIG. 3 shows a schematic circuit configuration of a delay line;

fig. 4 shows a schematic circuit configuration of one delay cell of the delay line;

fig. 5 is a schematic implementation flow diagram of a delay measurement method of a delay line according to an embodiment of the present application;

fig. 6 is a schematic implementation flow chart of a specific application example of a delay line delay measurement method according to an embodiment of the present application;

fig. 7 is a schematic diagram showing a composition structure of a delay measurement device of a delay line according to an embodiment of the present application;

fig. 8 is a schematic diagram showing the composition structure of a delay line delay measurement system according to an embodiment of the present application;

FIG. 9 shows a state transition diagram of a state machine based on dly_ms_ctrl of the delay measurement system shown in FIG. 8;

FIG. 10 illustrates a delay measurement circuit for a delay line provided by an embodiment of the present application;

fig. 11 shows a waveform diagram of an example of delay line delay measurement for a dly_code bit width of 8, 1T mode.

Detailed Description

The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are presented merely to enable one skilled in the art to better understand and practice the present application and are not intended to limit the scope of the present application in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The technical scheme of the present application is further elaborated below with reference to the drawings and specific embodiments.

First, in order to better explain the schemes of the embodiments of the present application, a simple description is first provided herein for an application scenario of the embodiments of the present application. A delay line is an element or device for delaying an electrical signal for a period of time, which is widely used in various interface circuits. For example, as shown in fig. 1, when a SoC (System on Chip) Chip reads data in a DDR memory, a delay line delay is required to delay the DQS signal by 1/4 clock cycle. FIG. 2 shows a timing diagram of the register sample setup and hold times of the DDR memory, as shown in FIG. 2, where the DDR memory returns to the edge aligned DQS and DQ [7:0] after receiving a read command sent from the SoC chip first. In order to meet the set-up and hold time of register sampling inside the SoC, it is necessary to delay DQS by 1/4 clock period to dqs_dly, and then sample DQ [7:0] with rising and falling edges of dqs_dly to obtain dq_pos and dq_neg, respectively, at this time, a delay line is required to realize the delay of DQS signal.

Next, the circuit configuration of the delay line will be briefly described here to explain the reason why the delay time measurement is performed on the delay line. The circuit structure of the delay line is as shown in fig. 3, din is a signal to be delayed; dout is the delayed signal; dly_code is a set of multi-bit signals used to control the delay size of the delay line. The delay line comprises a plurality of delay units (Dly _element) and a decoder (decoder). When dly_code=0, en [ n:0] =' b0 by the decoder; when dly_code=1, en [ n:0] =' b1; when dly_code=2, en [ n:0] =' b11; when dly_code=3, en [ n:0] =' b111; and so on. Wherein the circuit structure of one delay cell is shown in fig. 4.

From the above analysis, the delay time of the delay line and dly_code have a linear positive correlation, and the delay time of the delay line is increased by one delay unit (Dly _element) every 1 increment of dly_code. The step delay time of the delay line is the delay time of one delay cell (Dly _element). The delay time of a delay cell is related to the ambient temperature, voltage, etc. of the delay line, and is a dynamically changing parameter. Therefore, in the chip initialization stage, the delay time of the delay line equivalent to the target clock period needs to be measured, and the dly_code value corresponding to the equivalent delay time is recorded, so that different dly_code values are set for the delay line, and the expected delay time is obtained. For example, measuring a dly_code value corresponding to an equivalent delay time of one clock cycle T is 100, if a delay time of 1/4 clock cycle is required, the corresponding dly_code value is 25.

In view of this, the embodiment of the present application provides a delay line delay measurement method, and fig. 5 shows a schematic implementation flow diagram of the delay line delay measurement method provided in the embodiment of the present application.

Referring to fig. 5, the delay measurement method of the delay line in the embodiment of the present application at least includes the following operation flows: operation 501 of acquiring a measurement mode of a delay line for showing a target measurement time of the delay line and a bit width of a delay control signal of the delay line; an operation 502 of determining a pre-delay stage number of a delay control signal for controlling the delay line to implement delay according to the bit width; operation 503, judging the coincidence of the delay output result and the target measurement time under the action of the delay control signal corresponding to the pre-delay stage number; and step 504, adjusting the pre-delay level of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay level coincides with the target measurement time, thereby obtaining the delay level corresponding to the target measurement time.

In operation 501, a measurement mode of the delay line for showing a target measurement time of the delay line and a bit width of a delay control signal of the delay line are acquired.

In this embodiment of the present application, the measurement mode may include 0.25T, 0.5T, 1T, etc., where T represents one clock cycle of the delay line. The delay control signal may be represented by a set of binary digits, the bit width of which is the number of bits of the binary digit.

The measurement mode of the delay line is acquired here, so that delay time of 0.25T, 0.5T or 1T can be flexibly selected according to actual needs to perform measurement. Specifically, in a case where the signal transmission frequency of the interface circuit requiring the use of the delay line is low frequency, for example: 100M or 200M, the maximum delay time of the delay line is less than 1T, and then a 0.5T measurement mode is used; in a case where the signal transmission frequency of the interface circuit requiring use of the delay line is high frequency, for example: 1G, the maximum delay of the delay line is greater than 1T, using a 1T measurement mode. The selected 0.5T or 1T is called the target measurement time.

In operation 502, a pre-delay progression of a delay control signal that controls a delay line implementation delay is determined based on a bit width.

In this embodiment of the present application, the median of the delay control signal is taken as the pre-delay stage number according to the bit width, so as to determine the pre-delay stage number of the delay control signal for controlling the delay line to implement delay according to the bit width.

In this embodiment of the present application, taking the median of the delay control signal as the pre-delay stage number may be achieved by: the highest position of the delay control signal is 1 and the other positions are zero.

For example: the bit width of the delay control signal is 3, and here, the delay level may be directly taken as binary 100, i.e. the pre-delay level is 4.

The pre-delay stage number is to delay the line signal by accessing a delay unit corresponding to the pre-delay stage number, and detect whether the actual delay time corresponds to the target delay time.

In operation 503, the compliance of the delayed output result with the target measurement time under the action of the delay control signal corresponding to the pre-delay stage number is determined.

In this embodiment of the present application, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay progression. Accordingly, the following operations may be adopted to determine the compliance of the delayed output result under the action of the delayed control signal corresponding to the delay progression with the target measurement time: and judging the magnitude relation between the actual delay time and the target measurement time, and under the condition that magnitude relation obtained by two adjacent delay stages is opposite, judging that the delay output result is consistent with the target measurement time, and determining that the delay stage number of the delay control signal corresponding to one test with smaller delay difference in two adjacent tests is the delay stage number corresponding to the target measurement time. The delay difference is the difference between the actual delay time and the target measurement time.

Here, the delay progression most conforming to the target measurement time is determined by judging the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay progression and the target measurement time.

In operation 504, the pre-delay level of the delay control signal is adjusted according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay level coincides with the target measurement time, so as to obtain the delay level corresponding to the target measurement time.

In this embodiment of the present application, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay progression. Accordingly, the following operations may be employed to implement the pre-delay progression of the delay control signal according to compliance: when the actual delay time is greater than the target measurement time, the pre-delay progression is adjusted by adopting a dichotomy until the magnitude relation between the actual delay time and the target measurement time obtained by two adjacent delay progression is opposite.

In this embodiment of the present application, the adjustment of the pre-delay stage number by the dichotomy may be specifically implemented by: when the actual delay time is longer than the target measurement time, the position with the previous pre-delay stage number set to 1 is set to zero, other bits are kept unchanged, and when the actual delay time is shorter than the target measurement time, the position with the previous pre-delay stage number set to 1 is kept unchanged.

Therefore, the half-division method is adopted to gradually approach the target measurement time, so that the measurement speed is effectively increased, and the measurement time is shortened.

Fig. 6 is a schematic implementation flow chart of a specific application example of a delay line delay measurement method according to an embodiment of the present application.

Referring to fig. 6, a specific application example of the delay line delay measurement method provided in the embodiment of the present application at least includes the following operation flows:

in this embodiment of the present application, after determining the measurement mode of the 0.25T, 0.5T or 1T modes according to the measurement mode, the bit width of the delay control signal dly_code is first taken to be 1 at the highest position, and 0 at the other positions, and the highest position is unchanged when the delay time of the delay line is longer than the target delay time, and the second position 1 and the other positions are zero. Until the delay time of the delay line is not greater than the target delay time. And taking the delay series corresponding to the primary time with smaller difference between the actual delay time and the target delay time in the last two measurement processes as the final target delay series corresponding to the target delay time. Here, the target delay time here is consistent with the target measurement time concept above.

Thus, if dly_code bit width is n bits, the number of delay line steps controlled is n to the power of 2. And using a half-division method, and only traversing the dly_code n times in the process of measuring the delay time of the delay line to obtain a measurement result. For example, 256-level delay cells are 8 bits wide, and only 8 traversals of dly_code are needed to obtain the measurement result. Compared with the scheme that the measurement result can be obtained only by traversing 256 dly_codes in the prior art, the measurement time is effectively shortened.

Other implementation procedures of fig. 6 are similar to those of operations 501 to 504 in the embodiment shown in fig. 5, and will not be described herein.

According to the delay measurement method of the delay line, a measurement mode of the delay line and the bit width of a delay control signal of the delay line are obtained, the measurement mode is used for showing target measurement time of the delay line, the pre-delay level number of the delay control signal for controlling the delay line to realize delay is determined according to the bit width, the coincidence of a delay output result under the action of the delay control signal corresponding to the pre-delay level number and the target measurement time is judged, the pre-delay level number of the delay control signal is adjusted according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay level number coincides with the target measurement time, and the delay level number corresponding to the target measurement time is obtained. In this way, the measurement can be flexibly performed for different measurement modes, for example: the measurement can be performed in 0.25T, 0.5T or 1T modes respectively, wherein the measurement mode is not influenced by the clock duty ratio when being the 1T mode, and the measurement result is more accurate. Further, the pre-delay number of the delay control signal for realizing delay of the control delay line is determined according to the bit width, and the pre-delay number of the delay control signal is adjusted according to the coincidence of the delay output result under the action of the delay control signal corresponding to the pre-delay number and the target measurement time, so that the number of measurement turns can be remarkably reduced.

Similarly, based on the delay line delay measurement method, the embodiments of the present application further provide a computer readable storage medium storing a program, where when the program is executed by a processor, the program causes the processor to at least execute the following operation steps: operation 501 of acquiring a measurement mode of a delay line for showing a target measurement time of the delay line and a bit width of a delay control signal of the delay line; an operation 502 of determining a pre-delay stage number of a delay control signal for controlling the delay line to implement delay according to the bit width; operation 503, judging the coincidence of the delay output result and the target measurement time under the action of the delay control signal corresponding to the pre-delay stage number; and step 504, adjusting the pre-delay level of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay level coincides with the target measurement time, thereby obtaining the delay level corresponding to the target measurement time.

Further, based on the delay measurement method of the delay line as described above, the embodiment of the present application further provides a delay measurement device of the delay line, as shown in fig. 7, the device 70 includes: an acquisition module 701, configured to acquire a measurement mode of the delay line and a bit width of a delay control signal of the delay line, where the measurement mode is used to show a target measurement time of the delay line; a determining module 702, configured to determine a pre-delay stage number of a delay control signal for controlling the delay line to implement delay according to the bit width; a judging module 703, configured to judge the compliance of the delay output result and the target measurement time under the action of the delay control signal corresponding to the pre-delay stage number; and the adjusting module 704 is configured to adjust the pre-delay stage number of the delay control signal according to the compliance until the delay output result under the action of the delay control signal corresponding to the pre-delay stage number coincides with the target measurement time, so as to obtain a delay stage number corresponding to the target measurement time.

Still further, based on the delay measurement method of the delay line as described above, the embodiment of the present application further provides a delay measurement system of the delay line, as shown in fig. 8, where the system includes: the file register unit reg_file is used for receiving and storing a control file and a state file for measuring delay of the delay line; the delay detection circuit unit dly_ms is used for carrying out delay detection on the delay line based on the state file under the triggering of the measurement control unit and sending a delay output result; and the measurement control unit dly_ms_ctrl is used for acquiring a control file from the file registering unit, triggering the delay detection circuit unit to carry out delay detection, acquiring a delay output result from the delay detection circuit unit, and updating the state file according to the delay output result.

In this embodiment of the present application, the state file includes a measurement mode subfile for showing a target measurement time of the delay line and a bit width subfile for showing a bit width of the delay control signal; correspondingly, the measurement control unit updates the state file according to the delayed output result, and the measurement control unit comprises: determining a pre-delay stage number of a delay control signal for controlling the delay line to realize delay according to the bit width; judging the coincidence of a delay output result under the action of a delay control signal corresponding to the pre-delay stage number and the target measurement time; and adjusting the pre-delay stage number of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay stage number coincides with the target measurement time, and obtaining the delay stage number corresponding to the target measurement time.

The signals transmitted between the respective units are explained here as follows:

reg_access_bus: interface signals for reading and writing registers inside reg_file.

dly_ms_start: when the user configuration register triggers a delay time measurement, dly_ms_start will take effect (typically define 1 as an effective value and 0 as an inactive value).

dly_code_upd: the indication signal of dly_code is updated.

dly_code_upd_value: when dly_code_upd is valid, the dly_code register inside reg_file is updated to be a dly_code_upd_value.

dly_ms_finish: an indication signal of the end of the delay time measurement.

dly_ms_mode: to distinguish between the 0.5T and 1T delay time measurement modes. For example, dly_ms_mode equal to 0 may be defined as a 1T measurement mode, and dly_ms_mode equal to 1 as a 0.5T measurement mode.

dly_code: the number of delay stages of the delay line is controlled.

dly_ms_trig: after receiving the dly_ms_trig pulse, the pulse signal, dly_ms, measures the delay of the delay line corresponding to the current dly_code value.

dly_ms_result: the result of the current delay measurement, for example, when dly_ms_result is 0, indicates that the delay line delay time corresponding to the current dly_code value is greater than the target measurement time, and when dly_ms_result is 1, indicates that the delay line delay time corresponding to the current dly_code value is less than the target measurement time.

Further, in this embodiment of the present application, the file register unit reg_file is essentially a register file, and may include control registers and status registers required for delay measurement. The user can achieve the following objective by reading and writing reg_file: (1) triggering a delay time measurement of the delay line; (2) querying whether the delay measurement is complete; (3) querying the delay time measurement, i.e., dly_code value.

The measurement control unit dly_ms_ctrl is a control module that controls delay line delay time measurement, and fig. 9 shows a state transition diagram of a state machine based on dly_ms_ctrl of the delay measurement system shown in fig. 8.

Specific:

dly_ms_idle: an idle state. When the user triggers a delay measurement by configuring the register file, dly_code is restored to an initial value of 0 and the state machine jumps from the idle state to the dly_ms_code_upd state.

Half_code_set: this state updates the dly_code value in a dichotomy. For example, the bit width of dly_code is n, i.e., dly_code [ n-1:0]. After triggering the delay measurement, the first time HALF_CODE_SET is entered, dly_CODE [ n-1] is SET to 1, and the other bits of dly_CODE remain unchanged at an initial value of 0. The second entry to HALF_CODE_SET will SET dly_code [ n-2] to 1, and the other bits of dly_code remain unchanged. And so on, the nth entry HALF_CODE_SET SETs dly_CODE [0] to 1, and the other bits of dly_CODE remain unchanged.

Delay line delay time after the usual dly_code change requires waiting for a period of time to settle. The specific waiting time can be selected according to the actual situation or the waiting time is configured by the user.

Dly_ms_trig: in this state, the control module generates a pulse signal on the dly_ms_trig signal informing the dly_ms module to perform delay measurement.

DLY_MS_WAIT_RESULT waiting for the dly_ms module to return a valid dly_ms_result.

DLY_MS_CHECK_RESULT if dly_ms_result is 0, it means that the delay time of the delay line corresponding to the current dly_code value is longer than the target measurement time, and bit clear 0 where dly_code SET during the previous HALF_CODE_SET is SET to 1 is required. If dly_ms_result is 1, it indicates that the delay time of the delay line corresponding to the current dly_code value is smaller than the target measurement time, and the bit with dly_code SET to 1 in the previous HALF_CODE_SET period remains unchanged.

DLY_MS_FINISH if all bits of the dly_code have been traversed and the end state bit is entered, the control module generates a valid dly_ms_finish signal to the register module.

Fig. 10 illustrates a delay measurement circuit of a delay line according to an embodiment of the present application, where the interface circuit includes the delay measurement system described above.

In this embodiment of the present application, registers 1, 2, 3, 5 and 6 use the same clock clk_dly_ms, and the clock paths are equal in length. dly_ms_mode selects 1T measurement mode for 0, and the target measurement time is 1 clk_dly_ms clock cycle. dly_ms_mode selects the 0.5T measurement mode for 1, and the target measurement time is 0.5 clk_dly_ms clock cycles. Register 2 uses falling edge sampling and registers 1,3,4,5,6 use rising edge sampling. Register 1 is responsible for sampling dly_ms_trig one beat, with dly_ms_trig_r as the sampling result. dly_ms_trig_r passes through register 2, register 3, and MUX_1 becomes trig_dly_0.dly_ms_trig_r is changed to trig_dly1 through delay_line and MUX_0. Register 4 samples trig_dly1 with the rising edge of trig_dly0, and registers 5 and 6 are responsible for synchronizing the sampling result of register 4 to the clk_dlyms clock domain. Mux_0 functions to offset the delay of mux_1.

Fig. 11 shows a waveform diagram of an example of delay line delay measurement for a dly_code bit width of 8, 1T mode. As can be seen from the waveforms of the delay line delay measurement example of the dly_code bit width of 8, 1T mode in fig. 11, the final measurement result is: the delay of the delay line corresponding to dly_code [7:0] = 8' b0111_1110 is closest to 1 clk_dly_ms clock cycle.

It should be noted here that: the above description of the delay measurement device, system and interface circuit embodiments for the delay line is similar to the description of the method embodiments shown in fig. 1 to 6, and has similar advantages as the method embodiments shown in fig. 1 to 6, and therefore will not be repeated. For technical details not disclosed in the embodiments of the delay measurement device, the delay measurement system and the interface circuit of the delay line of the present application, please refer to the description of the method embodiments shown in fig. 1 to 6, which is described in the foregoing application, for saving space, and therefore, the description is not repeated.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of units is only one logical function division, and there may be other divisions in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.

Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partly contributing to the prior art, and the computer software product may be stored in a storage medium, and include several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A delay measurement method of a delay line, the method comprising:

acquiring a measurement mode of the delay line and a bit width of a delay control signal of the delay line, wherein the measurement mode is used for showing a target measurement time of the delay line;

determining a pre-delay stage number of a delay control signal for controlling the delay line to realize delay according to the bit width;

judging the coincidence of a delay output result under the action of a delay control signal corresponding to the pre-delay stage number and the target measurement time;

and adjusting the pre-delay progression of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay progression coincides with the target measurement time, so as to obtain the delay progression corresponding to the target measurement time.

2. The method of claim 1, determining a pre-delay stage of a delay control signal that controls the delay line to implement a delay according to the bit width, comprising:

and taking the median of the delay control signal as the pre-delay stage number according to the bit width.

3. The method of claim 2, the taking the median of the delay control signal as the pre-delay stage number, comprising:

and setting the highest position of the delay control signal to be 1 and setting the other positions to be zero.

4. The method of claim 1, the delay output result being used to show an actual delay time under the action of a delay control signal corresponding to the delay progression; in a corresponding manner,

the step of judging the coincidence of the delay output result under the action of the delay control signal corresponding to the delay progression and the target measurement time comprises the following steps:

judging the magnitude relation between the actual delay time and the target measurement time;

under the condition that the magnitude relation obtained by two adjacent delay series is opposite, judging that the delay output result is consistent with the target measurement time, and determining that the delay series of the delay control signal corresponding to one test with smaller delay difference in the two adjacent tests is the delay series corresponding to the target measurement time;

wherein the delay difference is the difference between the actual delay time and the target measurement time.

5. The method of claim 1, the delay output result being used to show an actual delay time under the action of a delay control signal corresponding to the delay progression; in a corresponding manner,

the adjusting the pre-delay stage number of the delay control signal according to the compliance includes:

and when the actual delay time is greater than the target measurement time, adopting a dichotomy to adjust the pre-delay progression until the magnitude relation between the actual delay time and the target measurement time obtained by two adjacent delay progression is opposite.

6. The method of claim 5, the adjusting the pre-delay stage using a dichotomy, comprising:

when the actual delay time is greater than the target measurement time, setting the position with 1 in the previous pre-delay stage number as zero, and keeping other bits unchanged;

and when the actual delay time is smaller than the target measurement time, the bit with the previous pre-delay stage number set to 1 is kept unchanged.

7. A delay measurement apparatus for a delay line, the apparatus comprising:

an acquisition module for acquiring a measurement mode of the delay line and a bit width of a delay control signal of the delay line, the measurement mode being used for showing a target measurement time of the delay line;

the determining module is used for determining the pre-delay series of the delay control signal for controlling the delay line to realize delay according to the bit width;

the judging module is used for judging the coincidence between the delay output result under the action of the delay control signal corresponding to the pre-delay stage number and the target measurement time;

and the adjusting module is used for adjusting the pre-delay progression of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay progression coincides with the target measurement time, so as to obtain the delay progression corresponding to the target measurement time.

8. A delay measurement system for a delay line, the system comprising:

the file registering unit is used for receiving and storing a control file and a state file for measuring the delay of the delay line;

the delay detection circuit unit is used for carrying out delay detection on the delay line based on the state file under the triggering of the measurement control unit and sending a delay output result;

and the measurement control unit is used for acquiring the control file from the file registering unit, triggering the delay detection circuit unit to carry out delay detection, acquiring the delay output result from the delay detection circuit unit, and updating the state file according to the delay output result.

9. The delay measurement system of claim 8, the status file comprising a measurement mode subfile for showing a target measurement time of the delay line and a bit width subfile for showing a bit width of a delay control signal; in a corresponding manner,

the measurement control unit updates the status file according to the delayed output result, including:

determining a pre-delay stage number of a delay control signal for controlling the delay line to realize delay according to the bit width;

judging the coincidence of a delay output result under the action of a delay control signal corresponding to the pre-delay stage number and the target measurement time;

and adjusting the pre-delay progression of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay progression coincides with the target measurement time, so as to obtain the delay progression corresponding to the target measurement time.

10. An interface circuit in need of delay measurement, the interface circuit comprising the delay measurement system of claim 8 or 9.