CN101217328A - Time synchronization method, system and device - Google Patents
Time synchronization method, system and device Download PDFInfo
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- CN101217328A CN101217328A CNA2007103085266A CN200710308526A CN101217328A CN 101217328 A CN101217328 A CN 101217328A CN A2007103085266 A CNA2007103085266 A CN A2007103085266A CN 200710308526 A CN200710308526 A CN 200710308526A CN 101217328 A CN101217328 A CN 101217328A
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Abstract
The invention discloses a time synchronization method, which is used for sending the synchronized time of a clock source to a unit to be synchronized, and the synchronized time consists of a high bit part and a lower bit part, a high-delay channel and a low-delay channel are arranged between the clock source and the unit to be synchronized; the high-delay channel is used for sending the high bit part of the synchronized time to the unit to be synchronized; and the low-delay channel is used for sending the lower bit part of the synchronized time to the unit to be synchronized; the unit to be synchronized acquires the lower bit part of the synchronized time that is currently transmitted from the low-delay channel after receiving the high bit part of the synchronized time; the high bit part and the lower bit part are combined into the local synchronized time. In addition, the invention further discloses a time synchronization system, clock source equipment and equipment to be synchronized. The invention can achieve the time synchronization with low cost and high precision.
Description
Technical field
The present invention relates to Time synchronization technique, be specifically related to method for synchronizing time, clock synchronization system, clock source device and treat synchronizer.
Background technology
In a lot of systems, require respectively to form in the system module time synchronized.For example, in network store system, be the important information that carries out storage lock in time, relies on can carry out operation such as data backup, disaster recovery accurately accurate lock in time.If system respectively forms and the lock in time of module occurs error, serious consequences such as loss of data, recovery failure then will appear in data recovery procedure.
Mainly adopt at present the clock source that is provided with in system, the mode by the tranmitting data register synch command realizes synchronously.Under this method of synchronization, clock source unit in the system sends the current time as being carried at lock in time in the clock synchronization order, this clock synchronization order is by the lock unit for the treatment of in the switching network arrival system, treat lock unit with the lock in time in the clock synchronization order as local lock in time, to realize the calibration of local clock.Wherein, 8: 45: 02 on the 12nd December in 2007 for example lock in time.But the method for synchronization shortcoming of this tranmitting data register synch command is, the clock synchronization order need be transmitted in the switching network in system, arrive each successively and treat lock unit, because the existence of propagation delay time, treat that lock unit receives the moment of lock in time and will be later than the moment that the clock source sends lock in time, treat that therefore the lock in time that lock unit receives is not accurate enough.Also just because of the existence of propagation delay time, each treats that lock unit can't receive the clock synchronization order simultaneously, causes different differences lock in time for the treatment of lock unit in the same system, synchronous error occurred.For example, be accurate to second the lock in time of clock synchronization order, so, the time for the treatment of lock unit 1 time of reception synch command in system is the moment 1, treats that the time of lock unit 2 time of reception synch command is the moment 2, and the saltus step of second took place between the moment 1 and the moment 2, then treat lock unit 1 and treat that the synchronous error between the lock unit 2 is 1 second, as seen, under this method of synchronization, timing tracking accuracy is not high enough.
A kind of high precision time synchronization scheme has appearred at present, but this scheme need be provided with the synchronizer such as global positioning system (GPS) receiver in system, each that is used for respectively giving system treats that lock unit sends lock in time, makes each treat that lock unit can receive accurate lock in time; This scheme can also be treated the GPS receiver all is set in the lock unit at each, treat that lock unit passes through the GPS receiver and receives the precise synchronization time, thereby the deadline is synchronous.But GPS receiver cost is higher, causes the realization cost of this time synchronized scheme higher.
Summary of the invention
In view of this, the invention provides a kind of method for synchronizing time, treat lock unit in order to send to the lock in time with the clock source, this method can realize low cost, high precision time synchronization.
Be made of high-order portion and low portion described lock in time, described clock source and treat to comprise between the lock unit high time delay passage and low time delay passage, and this method comprises:
By described high time delay passage to treating that lock unit sends the high-order portion of lock in time;
By described low time delay passage to treating that lock unit sends the low portion of lock in time;
When treating that lock unit receives the high-order portion of lock in time, obtain the low portion of the lock in time of current transmission from described low time delay passage; Described high-order portion and low portion are synthesized local lock in time.
Wherein, described lock in time high-order portion least unit greater than the maximum delay of described high time delay passage.Described high time delay passage is the network exchange passage, and described low time delay passage is a bus run.
Preferably, described by described low time delay passage to treating that the step that lock unit sends the low portion of lock in time further comprises: the data on the low time delay passage of order circulate between the low portion of 0 to described lock in time can be represented maximum time value and increase progressively.
Preferably, described before treating that lock unit sends the high-order portion of lock in time, further comprise: the low portion of judging current lock in time adds the maximum time value whether default maximum transmitted time delay can be represented more than or equal to the low portion of described lock in time, if, after the low portion saltus step of waiting for lock in time is 0, send the high-order portion that carries lock in time after the saltus step; Otherwise, directly carry out the described operation that sends the high-order portion of lock in time.
Preferably, the described high-order portion that sends by high time delay passage is to be carried in the lock in time that comprises high-order portion and low portion to send.
The present invention also provides a kind of clock synchronization system, treats lock unit in order to send to the lock in time with the clock source unit, and this system can realize low cost, high precision time synchronization.
This system comprises clock source unit and a plurality of lock unit for the treatment of, described clock source unit and respectively treat to comprise between the lock unit high time delay passage and low time delay passage; Be made of high-order portion and low portion described lock in time;
Described clock source unit is used for by described high time delay passage to treating that lock unit sends the high-order portion of lock in time; By described low time delay passage to treating that lock unit sends the low portion of lock in time;
The described lock unit for the treatment of, be used for when the high-order portion that receives from lock in time of described clock source unit, obtain the low portion of the lock in time of current transmission from described low time delay passage, high-order portion and the low portion that is obtained synthesized local lock in time.
Wherein, described clock source unit comprises high-order sending module and low level sending module;
Described high-order sending module, be used for the current time as lock in time, the high-order portion of lock in time is carried in the time synchronized order, send to by described high time delay passage and respectively treat lock unit, notice low level sending module;
Described low level sending module, be used under the notice of described high-order sending module, with the low portion of current time low portion as lock in time, be scaled the low time delay channel data of default coded format, send to by described low time delay passage and respectively treat lock unit.
Preferably, described low level sending module is further after sending low portion, and the data on the low time delay passage of order circulate between 0 to described low portion can be represented maximum time value and increase progressively.
Preferably, described clock source unit further comprises judge module, be used for before high-order sending module transmitting time synch command, judge that lock in time to be sent, low level added whether default maximum transmitted time delay surpasses the maximum time value that described lock in time, low portion can be represented, if, then determine to wait for, otherwise, determine to send; Judged result is sent to described high-order sending module;
Described high-order sending module further receives judged result, bides one's time for waiting when judgment result displays, after the low portion saltus step of waiting for lock in time is 0, sends the time synchronized order of carrying the high-order portion of lock in time after the saltus step; When judgment result displays sends, then directly carry out described transmit operation.
Wherein, the described lock unit for the treatment of comprises high-order acquisition module, low level acquisition module and synthesis module;
Described high-order acquisition module, the high-order portion that is used for being received from the lock in time of described clock source unit sends to described synthesis module, and notice low level acquisition module;
Described low level acquisition module is used for receiving when notice, reads the low delay channel data of default coded format from the low delay passage, obtains the low portion of lock in time through decoding, sends to synthesis module;
Described synthesis module is used for high-order portion and the low portion of described lock in time are synthesized local lock in time.
Wherein, described high time delay passage is the network exchange passage, and described low time delay passage is a bus run.Described bus run is serial bus channel or parallel bus passage.
The invention provides a kind of clock source device,, can realize low cost, high precision time synchronization in order to treating that lock unit provides lock in time.
Described clock source device and treat to comprise between the lock unit high time delay passage and low time delay passage; Be made of high-order portion and low portion described lock in time;
This equipment comprises high-order sending module and low level sending module;
Described high-order sending module is used for sending by described high time delay passage the high-order portion of lock in time, and notifies the low level sending module;
Described low level sending module is used under the notice of high-order sending module, sends the low portion of lock in time by described low time delay passage.
The invention provides a kind of synchronizer for the treatment of,, can realize low cost, high precision time synchronization in order to the lock in time that the receive clock source unit provides.
This treats to comprise between synchronizer and the clock source unit high time delay passage and low time delay passage; Be made of high-order portion and low portion described lock in time;
This treats that synchronizer comprises high-order acquisition module, low level acquisition module and synthesis module;
Described high-order acquisition module is used for receiving the high-order portion of lock in time from described high time delay passage, and sends to described synthesis module, and notice low level acquisition module;
Described low level acquisition module is used for reading the low portion of lock in time from described low time delay passage when receiving notice, sends to synthesis module;
Described synthesis module is used for high-order portion and the low portion of described lock in time of described lock in time are synthesized local lock in time.
According to above technical scheme as seen, the present invention will separately be transmitted lock in time, by high time delay channel transfer to the propagation delay time high-order portion of insensitive lock in time, by hanging down the time delay channel transfer to the propagation delay time low portion of very sensitive lock in time, treat that lock unit is when receiving the high-order portion of lock in time, with current synthetic with high-order portion, thereby obtain accurate this locality lock in time from low portion lock in time that low time delay passage obtains.Since on the low time delay passage lock in time low portion the transmission course time delay very low, even can ignore, therefore treat that lock unit can obtain accurate current lock in time of low portion, through with the combination of a high position, just obtain accurate lock in time, avoided the synchronous error that the propagation delay time of time synchronized order in system brought in the prior art.
Secondly, low time delay passage can be bus run, the present invention only need increase the bus that is used to send low portion lock in time in system so, has avoided prior art need increase the high problem of time synchronized cost that the synchronizer such as the GPS receiver brings.
Once more, the clock source is before sending high position lock in time, judge whether to carry out transmit operation again after needs are waited for saltus step lock in time according to current lock in time and default maximum transmitting time delay sum, thereby avoided big synchronous error because of lock in time, the unusual saltus step in process of transmitting caused.
In addition, when sending high-order portion, directly send the lock in time that comprises high-order portion and low portion, reduced modification original clock source device.
Description of drawings
Fig. 1 is the flow chart of method for synchronizing time in the embodiment of the invention.
Fig. 2 is the flow chart of method for synchronizing time in the preferred embodiment of the present invention.
Fig. 3 is the structural representation of clock synchronization system in the embodiment of the invention.
Fig. 4 is the structural representation of clock source device in the embodiment of the invention.
Fig. 5 is for treating the structural representation of synchronizer in the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing embodiment that develops simultaneously, describe the present invention.
The invention provides a kind of in order to send to the time synchronized scheme for the treatment of lock unit the lock in time with the clock source.In this scheme, be made of high-order portion and low portion lock in time, described clock source and treat to comprise between the lock unit high time delay passage and low time delay passage; By high time delay channel transfer to the propagation delay time high-order portion of insensitive lock in time, by hanging down the time delay channel transfer to the propagation delay time low portion of very sensitive lock in time, treat low portion and the combination of the high-order portion of lock in time of the lock in time on the low time delay passage of lock unit utilization, thereby obtain accurate local lock in time.
Wherein, at division high-order portion lock in time and low portion, make the maximum delay of the least unit of high-order portion lock in time greater than high time delay passage.So, lock in time, high-order portion can saltus step in the transmission course of high time delay passage, had avoided the synchronous error of high-order portion.In practice, when the clock source sends the high-order portion of lock in time, preferably, directly send the lock in time that comprises high-order portion and low portion, can reduce modification like this clock source device.
The time delay of transmission channel just is comparatively speaking.The present invention can adopt bus run or infrared ray passage to come the low portion of transmitting synchronous time as low time delay passage.With respect to bus run and infrared ray passage, the network exchange passage in order to the transmitting synchronous time is high time delay passage in the prior art.
Below be high time delay passage with the network exchange passage,, time synchronized scheme of the present invention is described in detail for low time delay passage is an example with bus run for embodiment.The clock source sends the lock in time that comprises high-order and low level by high time delay passage.
Fig. 1 is the flow chart of method for synchronizing time in the embodiment of the invention, and as shown in Figure 1, this method may further comprise the steps:
Step 101: when the clock source in the system sends lock in time by the network exchange passage, at self with the bus of respectively treating between the lock unit on the low portion of transmission lock in time, and refresh in real time.
In this step, be that the clock source is carried in the time synchronized order switching network by the place system and sends to and respectively treat lock unit lock in time.Lock in time, the figure place of low portion can be provided with flexibly according to concrete needs.
Step 102: when treating that lock unit receives lock in time, read the low portion of lock in time from bus.
Step 103: the lock in time that the low portion corrected received of the lock in time that utilization is read arrives, close and obtain local lock in time.
So far, this flow process finishes.
The form of lock in time is 8: 45: 02 on the 12nd December in 2007 for example, and be absolute time this lock in time.Certainly can also be the relative time with respect to a fiducial time lock in time among the present invention, for example 32582 seconds.
According to above-mentioned flow process, adopt the processing method of Fig. 1, utilize from bus reads current lock in time low portion to revising the lock in time that receives.Because refresh the lock in time on the bus in real time, it changed according to the time, always match with current lock in time, therefore each treats that lock unit can obtain lock in time accurately, has avoided the low problem of synchronization accuracy that the propagation delay time of time synchronized order in system brought in the prior art.With lock in time low portion be second to be example, treat lock unit when two differences and before and after position saltus step second, receive the time synchronized order of carrying 8: 45: 02 on the 12nd December in 2007 respectively, treat that lock unit can directly not utilize 8: 45: 02 on the 12nd December in 2007 as local lock in time for these two, but read a current second position from bus, the position of second in lock in time is revised in the position of the second that utilization is read, obtaining accurate local lock in time, thereby improved timing tracking accuracy.Simultaneously, this scheme only need increase the bus that is used to send low portion lock in time in system, has avoided prior art need increase the high problem of time synchronized cost that extra GPS receiver brings.
In practice, also can not adopt periodic refreshing low portion mode, but after the clock source sends high-order portion, the one section Preset Time of delaying time, after guaranteeing to treat that lock unit receives high-order portion, again with the current time as lock in time, send the low portion of lock in time.So, treat that lock unit utilizes the lock in time that the current low portion corrected received that reads arrives after, still can obtain accurate local lock in time.
Fig. 2 is the flow chart of method for synchronizing time in the preferred embodiment of the present invention.As shown in Figure 2, this method may further comprise the steps:
Step 201: the clock source in system and respectively treat to be provided with between the lock unit bus.
Step 202: treat lock unit by switching network to clock source transmitting time synchronization request.
Step 203: after the clock source receives request, send the time synchronized order of carrying lock in time, simultaneously the low level of lock in time is scaled the bus data of default coded format, on bus, transmit by switching network.
Wherein, default coded format can be specified according to actual needs, and for example 8421BCD coding, 2421BCD coding, 5421BCD encode, and Gray code or the like.Usually, can adopt 8421BCD coding comparatively commonly used as default coded format.The chronomere that the figure place of 8421BCD coding is represented according to the figure place and the low portion of low portion determines.If low portion be 1 and the expression second the position, its excursion is 0 to 9, adopts 4 8421BCD representation so; If low portion be 2 and the expression second ten and the position, its excursion is 0 to 59, adopts 6 8421BCD representation so; If low portion is ten and a position of 2 and expression millisecond, its excursion is 0 to 99, adopts 7 8421BCD representation so.
In order to reduce the length of bus transmitting data, preferably, with lock in time last the position as low portion lock in time.
In this step, bus can be universal serial bus or parallel bus.If the employing universal serial bus, then bus data serial transmission on same bus when reading bus data so, need be read the every of bus data successively on same bus, could obtain low portion lock in time.If the employing parallel bus, then bus data parallel transmission on many buses when reading bus data so, reads the every of bus data simultaneously on many buses, can obtain low portion lock in time.The radical of parallel bus is to determine according to the figure place of coded system and low portion.For example, if low portion is a position of 1 and expression second,, then need 4 buses to carry out parallel transmission if adopt 8421BCD coded representation low portion; If low portion is ten and a position of 2 and expression millisecond, then need 7 buses to carry out parallel transmission; In addition, clock source and treat that lock unit need consult the speed of transceiver bus data in advance.
Step 204: real-time refresh bus data make low portion lock in time on the bus circulate between low portion can be represented 0 to lock in time maximum time value and increase progressively.
In this step, if bus data is represented the position of second, the maximum time value that the individual potential energy of second is enough represented is 9 seconds, during the refresh bus data, from the units value of current second lock in time, increased progressively 1 every one second, the excursion of low level numerical value is 0 to 9 on the bus.
Step 205: after treating that lock unit receives the time synchronized order, therefrom obtain lock in time; Read the bus data of default coded format simultaneously from bus, obtain low portion lock in time by decoding.
Step 206: will be from low portion and synthesize local lock in time bus is obtained lock in time from the lock in time that the time synchronized order is obtained.
In practice, can comprise low level the lock in time in the time synchronized order, when so synthetic, will replace the corresponding low level of lock in time the time synchronized order from low portion lock in time that bus reads.Also can not comprise low level the lock in time in the time synchronized order, when so synthetic, merged as a high position and from low portion lock in time that bus is obtained the lock in time in the time synchronized order, constitutes local lock in time.
Treat that lock unit finishes local zone time and can notify the clock source to cancel low portion lock in time from bus synchronously.
From the above as seen, if in time synchronized command transfer process, low portion jumps to 0 from the maximum time value that can represent, treats that then lock unit will have very big-difference with the time of reality through the synthetic local lock in time that obtains, and produce big synchronous error.For example, be 15: 26: 49 on the 17th July in 2007 lock in time in the time synchronized order, lock in time, low portion was the position of second, in transmission course, data saltus step on the bus is 0, to obtain local zone time be 15: 26: 40 on the 17th July in 2007 through synthetic so, with 50 seconds of actual synchronization time very big-difference arranged, and unusual saltus step has taken place.
Cause occurring big synchronous error for fear of unusual saltus step, the present invention solves in the following way:
The clock source is before the transmitting time synch command, judge earlier lock in time to be sent, low portion added whether default maximum transmitted time delay surpasses the maximum time value that low portion can be represented, if wait for that then low portion saltus step lock in time is transmission again after 0, otherwise, directly send.Wherein, the maximum transmitted time delay can determine that the maximum transmitted time delay can not surpass 50ms usually according to the concrete condition of different system.
Be example for lock in time to be sent still with above-mentioned 2007 on July 17,15: 26: 49, supposing to preestablish the maximum transmitted time delay is 1 second, then before transmission, clock source inspection low portion lock in time added that the maximum transmitted time delay 1 second was 10 seconds in 9 seconds, the maximum time value that the individual potential energy that has surpassed second is enough represented, the low portion saltus step of then waiting for lock in time is 0, be after saltus step lock in time is 15: 26: 50 on the 17th July in 2007, carry out the transmission of lock in time again, thus the unusual saltus step of avoiding.
So far, this flow process finishes.
Cite an actual example below.Supposing the system is accurate to the position of second lock in time, adopts the default coded format of 8421BCD coding conduct, and 4 parallel bus transmitting synchronous time low portions are set.Lock in time is carried in the clock source in the time synchronized order be 15: 26: 47 on the 17th July in 2007, send to then request time synchronous treat lock unit, and the low level 7 of lock in time is converted to 8421BCD sign indicating number 0111 on 4 parallel buss, transmits, and begin real-time refresh bus data, make it pursue since 0111 and increase progressively second, excursion is 0000 to 1001; Treating that lock unit obtains lock in time simultaneously from the time synchronized order, obtain 8421BCD sign indicating number 1000 from 4 buses, obtain low level 8 through decoding, utilize low level 8 to revise 15: 26: 47 on the 17th July of 2007 lock in time of obtaining from the time synchronized order, obtaining local lock in time is 15: 26: 48 on the 17th July in 2007.As seen, this treats that it is accurately that lock unit obtains lock in time.Suppose to have simultaneously two module request times synchronous, and these two module time of reception synch command constantly 47 seconds to 48 seconds saltus step have taken place, but these two modules still can obtain local zone time accurately by reading bus data.
In order to realize method for synchronizing time of the present invention, the invention provides a kind of clock synchronization system, treat lock unit in order to send to the lock in time with the clock source.Fig. 3 is the structural representation of clock synchronization system among the present invention.As shown in Figure 3, this system comprises that clock source unit and m is treated lock unit, and wherein m is the integer more than or equal to 1.Clock source unit and treat to be provided with bus between the lock unit, bus is represented with heavy line in Fig. 3.Connect the clock source unit and represent to be used for the network exchange passage of transmission command and request with treating the fine line of lock unit.
Wherein, the clock source unit is used for by the network exchange passage to treating that lock unit sends lock in time, by self with treat that respectively bus between the lock unit is to treating the lock unit transmission low portion of lock in time.
Treat lock unit, be used for the lock in time that receives the self-clock source unit, reading the low portion of lock in time, the synthetic local lock in time of low portion lock in time of utilizing the lock in time of being obtained and reading from bus.
Particularly, Fig. 4 shows system clock source device in the embodiment of the invention, i.e. the structural representation of clock source unit among Fig. 3.As shown in Figure 4, this clock source device comprises high-order sending module and low level sending module, wherein,
High-order sending module, be used for receiving when treating the time synchronized request of lock unit, with the current time as lock in time, will be carried at lock in time in the time synchronized order, send to by the network exchange passage and respectively to treat synchronization module, and notice low level sending module.
The low level sending module is used under the notice of high-order sending module, and the low portion of the current time low portion as lock in time is transmitted on bus.Particularly, this low level sending module is after notified, and the bus data that low portion that at once should lock in time is scaled default coded format transmits on bus.And preferably, the real-time refresh bus data of this low level sending module make low portion lock in time on the bus circulate between low portion can be represented 0 to this lock in time maximum time value and increase progressively.Perhaps, this low level sending module is waited for one section Preset Time after notified, and then the operation that execution is obtained low portion and sent.Wherein, bus adopts heavy line to represent in Fig. 4.
In practice, as shown in Figure 4, this clock source device can further include judging unit, is used for obtaining the low portion of lock in time to be sent before high-order sending module transmitting time synch command, judge that low portion lock in time to be sent adds whether default maximum transmitted time delay surpasses the maximum time value that low portion can be represented, if, then determine to wait for, otherwise, determine to send, then judged result is sent to high-order sending module.
High-order sending module further receives judged result, when judgment result displays is bide one's time for waiting, after the low portion saltus step of waiting for lock in time is 0, sends the time synchronized order of carrying lock in time after the saltus step; When judgment result displays is transmission, then directly send the time synchronized order of carrying current lock in time.
Fig. 5 shows the synchronizer for the treatment of of system in the embodiment of the invention, promptly treats the structural representation of lock unit among Fig. 3.As shown in Figure 5, this treats that synchronizer comprises high-order acquisition module, low level acquisition module and synthesis module, wherein,
High-order acquisition module receives the time synchronized order of self-clock source unit, and therefrom extract lock in time and send to synthesis module, and notice low level acquisition module.
The low level acquisition module when receiving notice, reads the low portion of lock in time from bus, sends to synthesis module.Particularly, the low level acquisition module reads the bus data of default coded format from bus, and the row decoding of going forward side by side obtains the low portion of lock in time.When bus is universal serial bus, low level acquisition module order on the bus read bus data everybody, obtain corresponding decimal number through decoding, as low portion lock in time; When bus is parallel bus, the low level acquisition module read simultaneously on the many buses bus data everybody, obtain corresponding decimal number through decoding, as low portion lock in time.Wherein bus adopts heavy line to represent in Fig. 5.
Synthesis module is used to utilize from lock in time that the time synchronized order is obtained with from low portion lock in time that bus reads synthetic local lock in time.
By the above as can be seen, time synchronized scheme provided by the present invention can realize low cost, high precision time synchronization.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (19)
1. method for synchronizing time, treat to it is characterized in that lock unit that in order to send to the lock in time with the clock source be made of high-order portion and low portion described lock in time, described clock source and treat to comprise between the lock unit high time delay passage and low time delay passage, this method comprises:
By described high time delay passage to treating that lock unit sends the high-order portion of lock in time;
By described low time delay passage to treating that lock unit sends the low portion of lock in time;
When treating that lock unit receives the high-order portion of lock in time, obtain the low portion of the lock in time of current transmission from described low time delay passage; Described high-order portion and low portion are synthesized local lock in time.
2. the method for claim 1 is characterized in that, described lock in time high-order portion least unit greater than the maximum delay of described high time delay passage.
3. the method for claim 1 is characterized in that, described high time delay passage is the network exchange passage, and described low time delay passage is a bus run.
4. the method for claim 1, it is characterized in that, described by hanging down the time delay passage: as the low portion of described lock in time to be scaled the low time delay channel data of presetting coded format, on described low time delay passage, to transmit to treating that lock unit sends the low portion of lock in time and is;
Describedly obtain the low portion of the lock in time of current transmission from low time delay passage and be: read the low time delay channel data of default coded format from low time delay passage, obtain the low portion of described lock in time through decoding.
5. the method for claim 1, it is characterized in that, described by described low time delay passage to treating that the step that lock unit sends the low portion of lock in time further comprises: the data on the low time delay passage of order circulate between the low portion of 0 to described lock in time can be represented maximum time value and increase progressively.
6. the method for claim 1, it is characterized in that, described before treating that lock unit sends the high-order portion of lock in time, further comprise: the low portion of judging current lock in time adds the maximum time value whether default maximum transmitted time delay can be represented more than or equal to the low portion of described lock in time, if, after the low portion saltus step of waiting for lock in time is 0, send the high-order portion that carries lock in time after the saltus step; Otherwise, directly carry out the described operation that sends the high-order portion of lock in time.
7. the method for claim 1 is characterized in that, the described high-order portion that sends by high time delay passage is to be carried in the lock in time that comprises high-order portion and low portion to send.
8. clock synchronization system, comprise clock source unit and a plurality of lock unit for the treatment of, this system treats to it is characterized in that lock unit in order to send to the lock in time with the clock source unit, described clock source unit and respectively treat to comprise between the lock unit high time delay passage and low time delay passage; Be made of high-order portion and low portion described lock in time;
Described clock source unit is used for by described high time delay passage to treating that lock unit sends the high-order portion of lock in time; By described low time delay passage to treating that lock unit sends the low portion of lock in time;
The described lock unit for the treatment of, be used for when the high-order portion that receives from lock in time of described clock source unit, obtain the low portion of the lock in time of current transmission from described low time delay passage, high-order portion and the low portion that is obtained synthesized local lock in time.
9. system as claimed in claim 8 is characterized in that, described clock source unit comprises high-order sending module and low level sending module;
Described high-order sending module, be used for the current time as lock in time, the high-order portion of lock in time is carried in the time synchronized order, send to by described high time delay passage and respectively treat lock unit, notice low level sending module;
Described low level sending module, be used under the notice of described high-order sending module, with the low portion of current time low portion as lock in time, be scaled the low time delay channel data of default coded format, send to by described low time delay passage and respectively treat lock unit.
10. system as claimed in claim 9 is characterized in that, described low level sending module is further after sending low portion, and the data on the low time delay passage of order circulate between 0 to described low portion can be represented maximum time value and increase progressively.
11. system as claimed in claim 9 is characterized in that, described high-order sending module, and further the low portion with lock in time is carried in the described time synchronized order.
12. system as claimed in claim 9, it is characterized in that, described clock source unit further comprises judge module, be used for before high-order sending module transmitting time synch command, judge lock in time to be sent, low level added whether default maximum transmitted time delay surpasses the maximum time value that described lock in time, low portion can be represented, if then determine wait, otherwise, determine to send; Judged result is sent to described high-order sending module;
Described high-order sending module further receives judged result, bides one's time for waiting when judgment result displays, after the low portion saltus step of waiting for lock in time is 0, sends the time synchronized order of carrying the high-order portion of lock in time after the saltus step; When judgment result displays sends, then directly carry out described transmit operation.
13. system as claimed in claim 8 is characterized in that, the described lock unit for the treatment of comprises high-order acquisition module, low level acquisition module and synthesis module;
Described high-order acquisition module, the high-order portion that is used for being received from the lock in time of described clock source unit sends to described synthesis module, and notice low level acquisition module;
Described low level acquisition module is used for receiving when notice, reads the low delay channel data of default coded format from the low delay passage, obtains the low portion of lock in time through decoding, sends to synthesis module;
Described synthesis module is used for high-order portion and the low portion of described lock in time are synthesized local lock in time.
14., it is characterized in that described high time delay passage is the network exchange passage as any described system of claim 8 to 13, described low time delay passage is a bus run.
15. system as claimed in claim 14 is characterized in that, described bus run is serial bus channel or parallel bus passage.
16. a clock source device in order to treating that lock unit provides lock in time, is characterized in that, described clock source device and treat to comprise between the lock unit high time delay passage and low time delay passage; Be made of high-order portion and low portion described lock in time;
This equipment comprises high-order sending module and low level sending module;
Described high-order sending module is used for sending by described high time delay passage the high-order portion of lock in time, and notifies the low level sending module;
Described low level sending module is used under the notice of high-order sending module, sends the low portion of lock in time by described low time delay passage.
17. equipment as claimed in claim 16 is characterized in that, described low level sending module is further after sending described low portion, and the data on the low time delay passage of order circulate between 0 to described low portion can be represented maximum time value and increase progressively.
18. equipment as claimed in claim 16, it is characterized in that, this clock source device further comprises judge module, be used for before high-order sending module transmitting time synch command, judge lock in time to be sent, low level added whether default maximum transmitted time delay surpasses the maximum time value that described lock in time, low portion can be represented, if then determine wait, otherwise, determine to send; Judged result is sent to described high-order sending module;
Described high-order sending module further receives judged result, bides one's time for waiting when judgment result displays, after the low portion saltus step of waiting for lock in time is 0, sends the high-order portion of lock in time after the saltus step; When judgment result displays sends, then directly carry out described transmit operation.
19. treat synchronizer for one kind, it is characterized in that this treats to comprise between synchronizer and the clock source unit high time delay passage and low time delay passage the lock in time in order to the receive clock source unit provides; Be made of high-order portion and low portion described lock in time;
This treats that synchronizer comprises high-order acquisition module, low level acquisition module and synthesis module;
Described high-order acquisition module is used for receiving the high-order portion of lock in time from described high time delay passage, and sends to described synthesis module, and notice low level acquisition module;
Described low level acquisition module is used for reading the low portion of lock in time from described low time delay passage when receiving notice, sends to synthesis module;
Described synthesis module is used for high-order portion and the low portion of described lock in time of described lock in time are synthesized local lock in time.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007103085266A CN101217328B (en) | 2007-12-29 | 2007-12-29 | Time synchronization method, system and device |
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| CN2007103085266A CN101217328B (en) | 2007-12-29 | 2007-12-29 | Time synchronization method, system and device |
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| CN101217328A true CN101217328A (en) | 2008-07-09 |
| CN101217328B CN101217328B (en) | 2011-04-20 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102195996A (en) * | 2010-03-09 | 2011-09-21 | 杭州华三通信技术有限公司 | Time synchronization method for stacking system, stacking system and member equipment |
| CN102447561A (en) * | 2011-12-30 | 2012-05-09 | 深圳市文鼎创数据科技有限公司 | Input method and input device of system synchronous clock for dynamic token |
| CN107888315A (en) * | 2017-12-04 | 2018-04-06 | 清华大学 | A kind of method for synchronizing time |
| CN108234051A (en) * | 2016-12-15 | 2018-06-29 | 统捷通讯科技集团有限公司 | A kind of two-shipper method for synchronizing time |
| WO2018210277A1 (en) * | 2017-05-16 | 2018-11-22 | 中兴通讯股份有限公司 | Clock synchronization method and device, and computer storage medium |
| CN110475137A (en) * | 2019-09-06 | 2019-11-19 | 北京市博汇科技股份有限公司 | A kind of high-precision distribution is aobvious to control frame synchornization method and system |
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- 2007-12-29 CN CN2007103085266A patent/CN101217328B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102195996A (en) * | 2010-03-09 | 2011-09-21 | 杭州华三通信技术有限公司 | Time synchronization method for stacking system, stacking system and member equipment |
| CN102195996B (en) * | 2010-03-09 | 2013-06-26 | 杭州华三通信技术有限公司 | Time synchronization method for stacking system, stacking system and member equipment |
| CN102447561A (en) * | 2011-12-30 | 2012-05-09 | 深圳市文鼎创数据科技有限公司 | Input method and input device of system synchronous clock for dynamic token |
| CN108234051A (en) * | 2016-12-15 | 2018-06-29 | 统捷通讯科技集团有限公司 | A kind of two-shipper method for synchronizing time |
| WO2018210277A1 (en) * | 2017-05-16 | 2018-11-22 | 中兴通讯股份有限公司 | Clock synchronization method and device, and computer storage medium |
| CN107888315A (en) * | 2017-12-04 | 2018-04-06 | 清华大学 | A kind of method for synchronizing time |
| CN110475137A (en) * | 2019-09-06 | 2019-11-19 | 北京市博汇科技股份有限公司 | A kind of high-precision distribution is aobvious to control frame synchornization method and system |
| CN110475137B (en) * | 2019-09-06 | 2021-05-14 | 北京市博汇科技股份有限公司 | High-precision distributed display control frame synchronization method and system |
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|---|---|
| CN101217328B (en) | 2011-04-20 |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: Huasan Communication Technology Co., Ltd. |