Summary of the invention
In view of this, the object of the present invention is to provide a kind of clock synchronizing method, device and there is the radio frequency chip circuit of this device, to overcome that the dependence existed in prior art is strong, cost is high and the problem of waste power consumption.
A method for clock synchronous, comprising:
When radio frequency chip is in reset mode or corresponding module is non operating state, make the counter O reset of band Phase Processing;
When the counter of described band Phase Processing receives the signal of startup work, the high frequency clock of counter to the phase-locked loop pll circuit evolving received of described band Phase Processing carries out frequency division, and adjust initial phase, generate the first synchronised clock and export as required synchronised clock;
Whether the counter in the course of the work with Phase Processing described in real-time judge receives internal clock synchronization pulse;
If so, the counter of described band Phase Processing then enters horizontal phasing control with the rising edge of internal clocking for benchmark, generates the second synchronised clock and exports as required synchronised clock;
If not, judge whether the counter of described band Phase Processing receives external clock pulse, if so, the counter of described band Phase Processing then enters horizontal phasing control according to the rising edge of the external clock detected, generates the 3rd synchronizing clock signals and exports as required synchronised clock.
Preferably, the counter of described band Phase Processing enters horizontal phasing control with the rising edge of internal clocking for benchmark, generates the detailed process that the second synchronised clock exports as synchronised clock and comprises:
The counter of described band Phase Processing receives the current count value of the internal clocking that cycle counter sends;
Deduct at the current count value of described internal clocking on the basis of two required synchronous clocks, increase phase value adjustment phase place, obtain being the second synchronised clock that benchmark adjusts with the rising edge of described internal clocking; Described second synchronised clock is exported as required synchronised clock;
Wherein, described phase value can be on the occasion of or negative value, maximum is the half in target frequency cycle of described PLL circuit when producing high frequency clock, and the described target frequency cycle is the ratio of the high frequency clock frequency that produces of described PLL and target frequency.
Preferably, the counter of described band Phase Processing enters horizontal phasing control according to the rising edge of the external clock detected, generates the detailed process that the 3rd synchronised clock exports as required synchronised clock and comprises:
The counter of described band Phase Processing receives the outside external clock sent, and detects the rising edge of external clock via Edge check synchronizer;
Obtain target frequency cycle during described PLL circuit generation high frequency clock;
Deduct on the numerical value basis of high frequency clock required in synchronizing process at described target frequency cycle value, increase phase value adjustment phase place, obtaining is the 3rd synchronised clock that benchmark adjusts with the rising edge of described external clock;
Described 3rd synchronised clock is exported as required synchronised clock;
Wherein, the described target frequency cycle is the frequency of clock and the ratio of target frequency of described PLL circuit generation; Described phase value can be on the occasion of or negative value, maximum is the half in described target frequency cycle; The numerical value of high frequency clock required in synchronizing process is 4.
Preferably, the counter of described band Phase Processing without the need to the rising edge of the rising edge of internal clocking or external clock for benchmark enter horizontal phasing control time, generate the detailed process that the first synchronised clock exports as required synchronised clock and comprise:
Obtain target frequency cycle during described PLL generation high frequency clock;
On the basis of described target frequency cycle value, increase phase value adjustment phase place, obtain the first synchronised clock;
Described first synchronised clock is exported as required synchronised clock.
Preferably, the high frequency clock that described PLL circuit generates, its frequency is higher than required synchronised clock N clock doubly; Wherein, N is more than or equal to 3;
Or the frequency of the high frequency clock that described PLL circuit produces is the common multiple of the frequency of required synchronised clock.
A kind of clock synchronization apparatus, comprising: the counter of band Phase Processing, the cycle counter be connected with the counter of described band Phase Processing, and connects the counter of described band Phase Processing and the phase-locked loop pll circuit of described cycle counter;
Described PLL circuit, for generation of high frequency clock;
Described cycle counter, carries out frequency division for the high frequency clock described PLL circuit received produced, generates internal clocking; And to the phase count being with the counter of Phase Processing to provide internal clocking;
The counter of described band Phase Processing, for when radio frequency chip is in reset mode or corresponding module is in non operating state, quits work; When receiving the signal of startup work, carry out frequency division to the high frequency clock of the phase-locked loop pll circuit evolving received, initial phase is adjustable, generates the first synchronised clock and exports as required synchronised clock; And whether real-time judge receives internal clock synchronization pulse in the course of the work;
If so, then enter horizontal phasing control with the rising edge of internal clocking for benchmark, generate the second synchronised clock adjusted for benchmark using the rising edge of described internal clocking and export as required synchronised clock;
If not, judge whether again to receive external clock pulse, if so, then enter horizontal phasing control according to the rising edge of external clock detected, generate the 3rd synchronised clock adjusted for benchmark using the rising edge of described external clock and export as required synchronised clock.
Preferably, when the counter of described band Phase Processing receives internal clock synchronization pulse:
The counter of described band Phase Processing, for receiving the current count value of the internal clocking that cycle counter sends, deduct on the basis of two required synchronous clocks at the current count value of described internal clocking, increasing phase value adjustment phase place, exporting obtaining as required synchronised clock using the second synchronised clock that the rising edge of described internal clocking adjusts for benchmark;
Wherein, described phase value can be on the occasion of or negative value, maximum is the half in target frequency cycle of described PLL circuit when producing high frequency clock, and the described target frequency cycle is the ratio of the high frequency clock frequency that produces of described PLL and target frequency.
Preferably, when the counter of described band Phase Processing receives external clock pulse:
The counter of described band Phase Processing, for obtaining target frequency cycle during described PLL circuit generation high frequency clock; To deduct in synchronizing process at described target frequency cycle value on the numerical value basis of required high frequency clock, increase phase value adjustment phase place, the 3rd synchronised clock adjusted for benchmark using described external clock rising edge obtained is exported as required synchronised clock;
Wherein, the rising edge information of described external clock obtains via Edge check synchronizer; The described target frequency cycle be described PLL circuit produce the frequency of clock and the ratio of target frequency; Described phase value can be on the occasion of or negative value, maximum is the half in described target frequency cycle; The numerical value of high frequency clock required in synchronizing process is 4;
Or, described second synchronised clock is postponed export as required synchronised clock after a bat.
Preferably, the high frequency clock that described PLL circuit generates, it is that frequency is higher than required synchronised clock N clock doubly; Wherein, N is more than or equal to 3;
Or the frequency of the high frequency clock that described PLL circuit produces is the common multiple of the frequency of required synchronised clock.
A kind of radio frequency chip circuit, comprising: clock synchronization apparatus and Edge check synchronizer;
Described clock synchronization apparatus is above-mentioned disclosed any one clock synchronization apparatus;
Described Edge check synchronizer, for when carrying out external clock, detects the rising edge of external clock, and then generates external clock pulse; When carrying out internal clock synchronization, detect the rising edge of internal clocking, and then generate internal clock synchronization pulse.
Owing to embodiments providing a kind of clock synchronizing method, device and there is the radio frequency chip circuit of this device.The present invention is by resetting at radio frequency chip or in the idle situation of corresponding module, making the counter O reset of band Phase Processing namely quit work, and generating synchronizing clock signals is that 0 level is to reduce the power consumption of radio frequency chip; Generate synchronizing clock signals when receiving internal clock synchronization pulse, its phase place can adjust according to internal clock rising edge; This synchronised clock is when receiving external clock pulse, and its phase place can adjust according to external clock rising edge; Simultaneously, when not receiving internal clock synchronization pulse and external clock pulse, namely do not rely on inside, when also not relying on external reference clock, make the counter of band Phase Processing generate the generation synchronizing clock signals of phase-adjustable by multiplexing PLL circuit.Phase-adjustable ensure that the phase relation of clock edge and data, makes radio frequency chip can correctly receive the data that need launch, and can realize low dependence, low cost and the object of low-power consumption by method disclosed in the invention described above.
Embodiment
A kind of clock synchronizing method that the embodiment of the present invention provides, device and there is the radio frequency chip circuit of this device, by for receiving internal clock synchronization pulse, or for receiving external clock pulse, or for when not receiving internal clock synchronization pulse and external clock pulse, adjust phase place as the case may be and generate required synchronised clock, low dependence, low cost and the object of low-power consumption can be realized.
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
As shown in Figure 1, a kind of clock synchronization apparatus disclosed in this embodiment of the invention, mainly comprises: the counter 13 of PLL (phase-locked loop) circuit 11, cycle counter 12 and band Phase Processing.
Wherein, be connected between cycle counter 12 with the counter 13 of band Phase Processing; PLL circuit 11 connects the counter 13 of cycle counter 12 and band Phase Processing simultaneously.
This PLL circuit 11, for generation of high frequency clock H_clk.
This cycle counter 12, carries out frequency division for the high frequency clock H_clk PLL circuit of reception produced, and generates internal clocking M_clk.This cycle counter 12 is to the count value of internal clocking should carrying out the reference phase of internal clock synchronization as the counter 13 of band Phase Processing.In addition, the frequency of this internal clocking M_clk can as the target frequency of high frequency clock H_clk.
The counter 13 of this band Phase Processing, resetting for being in when radio frequency chip when reset mode or corresponding module are in non operating state, namely quitting work.Above-mentioned corresponding module generally refers to radiating circuit module.(i.e. the phase value of internal clocking)
When the counter 13 of this band Phase Processing receives the signal of startup work, the counter 13 of this band Phase Processing carries out frequency division to the high frequency clock H_clk that the PLL circuit 11 received generates, initial phase is adjustable, generates the first synchronised clock and exports as required synchronised clock L_clk.
In the process of specific works, whether the counter of this band Phase Processing of real-time judge receives internal clock synchronization pulse, if so, then enter horizontal phasing control with the rising edge of internal clocking for benchmark, generate the second synchronised clock and export as required synchronised clock L_clk.
If not, then judge whether the counter 13 of this band Phase Processing receives external clock pulse, if so, then the rising edge according to the external clock detected enters horizontal phasing control, generates the 3rd synchronised clock and exports as required synchronised clock L_clk.
It should be noted that, the high frequency clock H_clk that above-mentioned PLL circuit 11 generates, it is that frequency is higher than required synchronised clock L_clkN clock doubly; Wherein, N is more than or equal to 3.
Or the frequency of the high frequency clock H_clk that this PLL circuit 11 produces is the common multiple of the frequency of required synchronised clock L_clk.
Counter 13 for above-mentioned band Phase Processing receives internal clock synchronization pulse, or for receiving external clock pulse, or for when not receiving internal clock synchronization pulse and external clock pulse, be specifically described below.
One, receives internal clock synchronization pulse.
This embodiment of the invention is being carried out in the process of clock synchronous based on disclosed clock synchronization apparatus, when the counter 13 of this band Phase Processing receives internal clock synchronization pulse, the counter 13 of this band Phase Processing is mainly used in the internal clocking M_clk receiving cycle counter 12 transmission, in fact the current count value for internal clocking M_clk received, the i.e. phase value of internal clocking, and on the basis of two clocks synchronous needed for deducting at described internal clocking phase value Mclk_cnt (these two clocks are actually the numerical value of high frequency clock required in synchronizing process) (Mclk_cnt-2), increase phase value adjustment phase place, using obtain with internal clock rising edge be reference phase adjustment the second synchronised clock export as required synchronised clock L_clk.
Wherein, the phase value of increase can be on the occasion of or negative value, maximum is the half in the target frequency cycle of PLL circuit 11 when producing high frequency clock H_clk, and the described target frequency cycle is the ratio of the high frequency clock frequency that produces of described PLL and target frequency.Such as, the clock frequency of the high frequency clock H_clk that PLL circuit 11 produces is 491.52MHz, target frequency is 3.84MHz, then there are 128 pll clock cycles in the target frequency cycle, half target frequency cycle is then 64, and the phase number of required adjustment is maximum can be positive 64 or negative 64 (utilizing highest order to represent sign in the process of carrying out cycle count).
Its two, receive external clock pulse.
When the counter 13 of described band Phase Processing receives external clock pulse, the counter 13 of this band Phase Processing is mainly used in obtaining target frequency cycle when PLL circuit 11 produces high frequency clock H_clk; Deduct on the numerical value basis of required high frequency clock in synchronizing process at this target frequency cycle value, increase and need the phase value (offset_delay) of adjustment to adjust phase place, the 3rd synchronised clock adjusted for benchmark using described external clock rising edge obtained is exported as required synchronised clock L_clk.
Wherein, the rising edge information of described external clock obtains via Edge check synchronizer; The described target frequency cycle is the high frequency clock frequency of this PLL circuit 11 generation and the ratio of target frequency; Described phase value can be on the occasion of or negative value, maximum is the half in described target frequency cycle; The numerical value of high frequency clock H_clk required in synchronizing process is 4.
Counter 13 for above-mentioned band Phase Processing carries out the process of external clock when receiving external clock pulse, the clock frequency of the high frequency clock H_clk produced when PLL circuit 11 is 491.52MHz, target frequency is 3.84MHz, then there are 128 pll clock cycles (being expressed as 0 ~ 127) in the target frequency cycle, half target frequency cycle is then 64, and the phase number of required adjustment is maximum can be positive 64 or negative 64 (utilizing highest order to represent sign in the process of carrying out cycle count).Concrete phase place is adjusted to (127-4+offset_delay).
As shown in Figure 2, the structural representation of Edge check synchronizer disclosed in the embodiment of the present invention, mainly comprises: the D register (D1, D2, D3) of three cascades, one not gate F1 and and door Y1.
Concrete structure is that D1, D2, D3 carry out cascade by in-phase output end and D input successively, the required clock G_clk detected of input input of D1, and the input end of clock of each D register then inputs H_clk respectively; The in-phase output end of D3 is connected with an input of door Y1 by not gate F1, should with another input of door Y1 then with the D register of cascade second level output be connected, namely be connected with the in-phase output end of D2, the output finally by this and door Y1 exports G_clk_pos.Wherein, when current required detect be external clock time, G_clk is external clock F_clk, final export be G_clk_pos actual be F_clk_pos; When current required detect be internal clocking time, G_clk is internal clocking M_clk, and the G_clk_pos of final output is actual is M_clk_pos.
Disclosed in this Edge check synchronizer and the invention described above embodiment, clock synchronization apparatus can be arranged in radio frequency chip circuit simultaneously, and the PLL circuit wherein in clock synchronization apparatus and cycle counter adopt multiplexing mode to use.
When carrying out external clock when being with the counter 13 of Phase Processing to receive external clock pulse, such as, the high-frequency clock H_clk that PLL circuit 11 generates, its frequency is required synchronised clock L_clk*N, and wherein N is greater than 3.When the frequency of the high-frequency clock H_clk adopted is 491.52MHz, now, optional synchronised clock L_clk is the requirement meeting LTE, is chosen as 61.44MHz, 46.08MHz, 23.04MHz, 30.72MHz, 3.84MHz etc.
As can be seen from Figure 2, synchronous required H_clk is 3 clocks.In practical application, the generation of synchronised clock L_clk has used d type flip flop to postpone a bat, so total synchronised clock is 4 H_clk clocks.Time synchronous, target frequency cycle value is deducted the numerical value of the high frequency clock in synchronizing process, and then add the numerical value (offset_delay) that need adjust phase place, thus obtain the initial phase of required synchronised clock L_clk.
According to the synchronised clock L_clk that the result of the counter of band Phase Processing generates, this synchronised clock can directly generate or with D register delay one bat.
Its three, do not receive internal clock synchronization pulse and external clock pulse.
When being with the counter 13 of Phase Processing not receive described internal clock synchronization pulse and external clock pulse, namely the counter 13 with Phase Processing without the need to the rising edge of the rising edge of internal clocking or external clock for benchmark adjustment phase place time, frequency division is carried out to the high frequency clock H_clk that the PLL circuit 11 received generates, generates the first synchronised clock and export as required synchronised clock.Concrete is with the counter 13 of Phase Processing to carry out cycle count for utilizing, and the count value produced is exported as synchronised clock L_clk.Or, utilize the counter 13 of band Phase Processing to obtain target frequency cycle when PLL circuit 11 produces high frequency clock H_clk; On the basis of described target frequency cycle value, increase phase value adjustment phase place, obtain the first synchronised clock; Described first synchronised clock is exported as required synchronised clock L_clk.
It should be noted that, above-mentioned Edge check synchronizer, when carrying out external clock, detects the rising edge of external clock, and then generates external clock pulse; When carrying out internal clock synchronization, detect the rising edge of internal clocking, and then generate internal clock synchronization pulse.
Clock synchronization apparatus and radio frequency chip circuit disclosed in the invention described above embodiment, when radio frequency chip resets and/or corresponding module is in inoperative, namely the counter O reset of band Phase Processing quits work, to reduce the power consumption of radio frequency chip; When receiving internal clock synchronization pulse or external clock pulse, as the case may be with the rising edge of inner or external clock for benchmark adjusts phase place, generate required synchronised clock, to obtain correct clock edge and the phase relation of data, make radio frequency chip correctly can receive data.
Simultaneously, when not receiving internal clock synchronization pulse and external clock pulse, when namely not relying on inside and outside reference clock, make the counter of band Phase Processing generate required synchronised clock by multiplexing PLL circuit, thus realize low dependence, low cost and the object of low-power consumption.
Embodiment two
On the basis of clock synchronization apparatus and radio frequency chip circuit disclosed in the invention described above embodiment, as shown in Figure 3, the embodiment of the present invention is the corresponding a kind of method disclosing clock synchronous also, mainly comprises the following steps:
Step S101, powers on, and judges whether current radio frequency chip is in reset mode, if so, then makes the counter O reset of band Phase Processing; If not, then step S102 is performed.
Step S102, judges whether corresponding module is in non operating state, if so, then makes the counter O reset of band Phase Processing; If not, then step S103 is performed.Wherein, corresponding module generally refers to the transmitter module in radio frequency chip.
Step S103, judge whether the counter of described band Phase Processing receives the pulse signal of startup work, if, the high frequency clock of counter to the phase-locked loop pll circuit evolving received of described band Phase Processing carries out frequency division, adjust initial phase simultaneously, generate the first synchronised clock to export as required synchronised clock, wherein, carry out initial phase adjustment excessively in, by needing the phase value tx_cnt assignment of generated clock L_clk to be phase adjustment value offset1, carry out the adjustment of initial phase according to this phase adjustment value offset1.If not, then S104 is performed.
Step S104, judges whether the counter of described band Phase Processing receives internal clock synchronization pulse; If, then the counter of described band Phase Processing then with the rising edge of internal clocking for benchmark enters horizontal phasing control, generate the second synchronised clock to export as required synchronised clock, wherein, the process entering horizontal phasing control is, is that the phase value mclk_cnt of internal clocking deducts required two synchronous H_clk clocks and adds phase adjustment value offset_2 by needing the phase value tx_cnt assignment of generated clock L_clk; If not, then step S105 is performed.
Step S105, judge whether the counter of described band Phase Processing receives external clock pulse, if, then the counter of described band Phase Processing then enters horizontal phasing control according to the rising edge of the external clock detected, generate the 3rd synchronised clock to export as required synchronised clock, wherein, the process entering horizontal phasing control is, is 127-4+offset_delay by needing the phase value tx_cnt assignment of generated clock L_clk; If not, then step S106 is performed.
Step S106, the counter of described band Phase Processing carries out cycle count.Be specially: with the rising edge of the high frequency clock H_clk of the PLL circuit received generation for benchmark subtracts 1 computing to tx_cnt.The result of tx_cnt is for generating required synchronised clock L_clk.
In step S101 ~ step S106 disclosed in the invention described above embodiment, the clock frequency of high-frequency clock H_clk is N times of synchronised clock L_clk, and this N is more than or equal to 3; Or the clock frequency of high-frequency clock H_clk is the common multiple of the synchronised clock L_clk generated.
It should be noted that, the detailed process of above-mentioned steps S104 comprises:
First, the counter of described band Phase Processing receives the phase value of the internal work benchmark M_clk clock that cycle counter sends.
Be specially: cycle counter receives the high frequency clock signal H_clk that PLL circuit sends, and carries out frequency division to it, generate internal clocking M_clk; Using the phase value of its count value mclk_cnt as internal clocking M_clk.
Secondly, on the basis that the phase value basis of described internal clocking M_clk deducts two H_clk clocks needed for synchronous rising edge (mclk_cnt-2), increase phase value adjustment phase place, obtain the initial phase of required synchronised clock;
Finally, the second synchronised clock of the generation carried out after initial phase adjustment is exported as required synchronizing clock signals L_clk.
Wherein, described phase value can be on the occasion of or negative value, maximum is the half in target frequency cycle of described PLL circuit when producing high frequency clock signal H_clk, and the described target frequency cycle is the ratio of the high frequency clock frequency that produces of described PLL and target frequency.
The detailed process of above-mentioned steps S105 is:
First, the counter of described band Phase Processing receives the outside external clock F_clk sent, and detects the rising edge of described external clock F_clk via Edge check synchronizer.
Secondly, target frequency cycle during described PLL circuit generation high frequency clock signal H_clk is obtained.
Secondly, deduct at described target frequency cycle value on the basis of the numerical value of high frequency clock H_clk required in synchronizing process, increase phase value adjustment phase place, obtain with the initial phase of described external clock F_clk rising edge synchronised clock needed for benchmark.
Finally, export carrying out rear the 3rd synchronised clock generated of initial phase adjustment as required synchronised clock L_clk.
Wherein, the described target frequency cycle is the frequency of high frequency clock H_clk and the ratio of target frequency of described PLL circuit generation; Described phase value can be on the occasion of or negative value, maximum is the half in described target frequency cycle; The numerical value of high frequency clock required in synchronizing process is 4.
In step S106, can also comprise: the synchronised clock generated by described tx_cnt exports as required synchronised clock L_clk after postponing a bat.
Be described for said process citing, when the frequency of high-frequency clock H_clk is 491.52MHz, target frequency is 3.84MHz.The target frequency cycle is that 128 (be expressed as: 0 ~ 127), half target frequency cycle is 64.Phase value is maximum can be adjusted to+64 or-64.The frequency of optional synchronizing clock signals L_clk is 61.44MHz, 46.08MHz, 23.04MHz, 30.72MHz and 3.84MHz.Corresponding N value is respectively 8,12,6,16 and 128.
On the basis of clock synchronizing method disclosed in the invention described above embodiment, the verilog descriptive statement of the counter phase adjustment of band Phase Processing can be:
The verilog descriptive statement of L_clk generative circuit is as follows:
Its hardware bearing part of clock synchronizing method disclosed in this embodiment of the invention described above is above-mentioned disclosed clock synchronization apparatus, and both concrete implementations are identical can cross-reference.
In actual applications, disclosed in application the invention described above, disclosed in embodiment, method and apparatus carries out in the process of clock synchronous, can select as required to be carry out internal clock synchronization, still external clock is carried out, or outside and inside are not considered, independently generates synchronised clock.It should be noted that, each application only can select a kind of situation to carry out clock synchronous.
In sum, a kind of clock synchronizing method, device disclosed in the above embodiment of the present invention and there is the radio frequency chip circuit of this device, by under radio frequency chip reset and/or the idle situation of corresponding module, namely the counter O reset of band Phase Processing is quit work, to reduce the power consumption of radio frequency chip; Generate synchronizing clock signals when receiving internal clock synchronization pulse, its phase place can adjust according to internal clocking; This synchronised clock is when receiving external clock pulse, and its phase place can adjust according to external clock; Meanwhile, when not receiving internal clock synchronization pulse and external clock pulse, namely not relying on inside, when also not relying on external reference clock, also can generate the generation synchronised clock of phase-adjustable.Phase-adjustable ensure that the phase relation of clock edge and data, makes radio frequency chip correctly can receive data.
Low dependence, low cost and the object of low-power consumption can be realized by method disclosed in the invention described above.
Below be only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can directly use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.