CN202650547U - Register circuit module - Google Patents
Register circuit module Download PDFInfo
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- CN202650547U CN202650547U CN 201220233413 CN201220233413U CN202650547U CN 202650547 U CN202650547 U CN 202650547U CN 201220233413 CN201220233413 CN 201220233413 CN 201220233413 U CN201220233413 U CN 201220233413U CN 202650547 U CN202650547 U CN 202650547U
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Abstract
The utility model discloses a register circuit module. The register circuit module comprises a communication circuit, a register unit, a debugging circuit, a rapid reset circuit and an output circuit, wherein the communication circuit, the debugging circuit, the register unit and the output circuit are connected in sequence; the rapid reset circuit is connected on the register unit in parallel and comprises a resetting circuit and a signal reset circuit; and the output circuit is connected with a noise reduction circuit. With the adoption of the register circuit module disclosed by the utility model, circuit power consumption can be reduced, and circuit stability and availability are high.
Description
Technical field
The utility model relates to integrated circuit fields, particularly relates to a kind of register circuit module.
Background technology
For the consideration to system stability and cost, market proposes more and more higher requirement to function and the performance of chip.System-level user wishes the design complexity of reduce circuit system, requires simultaneously simple as far as possible chip periphery circuit.This causes the day by day increase of the scale of modern integrated circuits so that increasing function is integrated in the chip.For fear of mistake register is set, improves the reliability of system, at present, two schemes is arranged, and a kind of scheme is to increase the redundant hardware components and parts in system, and the hardware of realizing a certain function is backed up, when main circuit is unusual, starts stand-by circuit and take over main circuit work.Another program is to increase reliability of software, is the supervising devices such as increase house dog such as controller.
The function of modern monster chip is very complicated, for example, for enlarge range of application require to comprise several interfaces of realizing same function, for the function that improves the most of modules of requirement on flexibility can independent switch, in addition bus bit wide and the isoparametric selection of travelling speed etc., these functions all need corresponding register to dispose.It is very common to contain thousands of configuration registers in the chip.In order to keep good compatibility, these registers generally pass through I
2C interface disposes.In order to improve configuration speed, the General System main equipment can use quick mode even fast mode to visit these registers.In order to meet I
2The standard of C, the system clock frequency that offers the chip configuration register module should be in the magnitude of hundred megahertzes.So, even closing all functions, chip is in the stand-by energy-saving pattern, the power consumption of configuration register module itself also is very considerable, especially for the exigent handheld mobile device of power consumption.Continuing under the normal operation, after register configuration was complete, this module was in a kind of relatively static state, if also can manage to reduce during this period the power consumption of this module, for the cruising time of improving equipment be highly significant.Also can reduce the thermal value of chip in the time of power-dissipation-reduced, can improve reliability and the serviceable life of system.
The utility model content
The technical matters that the utility model mainly solves provides a kind of register circuit module, can reduce the power consumption of circuit, and stability is strong, and availability is high.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of register circuit module is provided, comprise: telecommunication circuit, register cell, debug circuit, quick-reset circuit and output circuit, described telecommunication circuit, debug circuit, register cell and output circuit are connected successively, described quick-reset circuit is connected in parallel on the register cell, described quick-reset circuit comprises reset circuit and signal reset circuit, is connected with Dolby circuit on the described output circuit.
In preferred embodiment of the utility model, described telecommunication circuit comprises transmission unit, clock control cell and digital dock generating unit.
In preferred embodiment of the utility model, described debug circuit comprises signal differential unit, main control unit and protected location.
In preferred embodiment of the utility model, described register cell comprises wave filter, I
2C SLAVE and a plurality of register.
The beneficial effects of the utility model are: the utility model register circuit module, can reduce the power consumption of circuit, and stability is strong, and availability is high.
Description of drawings
Fig. 1 is the structural representation of the utility model register circuit module one preferred embodiment;
The mark of each parts is as follows in the accompanying drawing: 1, telecommunication circuit, 2, register circuit, 3, debug circuit, 4, quick-reset circuit, 5, output circuit, 6, Dolby circuit, 7, reset circuit, 8, the signal reset circuit.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present utility model is described in detail, thereby so that advantage of the present utility model and feature can be easier to be it will be appreciated by those skilled in the art that protection domain of the present utility model is made more explicit defining.
See also Fig. 1, a kind of register circuit module, comprise: telecommunication circuit 1, register cell 2, debug circuit 3, quick-reset circuit 4 and output circuit 5, described telecommunication circuit 1, debug circuit 3, register cell 2 and output circuit 5 are connected successively, described quick-reset circuit 4 is connected in parallel on the register cell 3, described quick-reset circuit 4 comprises reset circuit 7 and signal reset circuit 8, and 5 are connected with Dolby circuit 6 on the described output circuit.
In addition, described telecommunication circuit 1 comprises transmission unit, clock control cell and digital dock generating unit.
In addition, described debug circuit 3 comprises signal differential unit, main control unit and protected location.
In addition, described register cell 2 comprises wave filter, I
2C SLAVE and a plurality of register.
Be different from prior art, the utility model register circuit module can reduce the power consumption of circuit, and stability is strong, and availability is high.
The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model instructions and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.
Claims (4)
1. register circuit module, it is characterized in that, comprise: telecommunication circuit, register cell, debug circuit, quick-reset circuit and output circuit, described telecommunication circuit, debug circuit, register cell and output circuit are connected successively, described quick-reset circuit is connected in parallel on the register cell, described quick-reset circuit comprises reset circuit and signal reset circuit, is connected with Dolby circuit on the described output circuit.
2. register circuit module according to claim 1 is characterized in that, described telecommunication circuit comprises transmission unit, clock control cell and digital dock generating unit.
3. register circuit module according to claim 1 is characterized in that, described debug circuit comprises signal differential unit, main control unit and protected location.
4. register circuit module according to claim 1 is characterized in that, described register cell comprises wave filter, I
2C SLAVE and a plurality of register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220233413 CN202650547U (en) | 2012-05-23 | 2012-05-23 | Register circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220233413 CN202650547U (en) | 2012-05-23 | 2012-05-23 | Register circuit module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202650547U true CN202650547U (en) | 2013-01-02 |
Family
ID=47419615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220233413 Expired - Fee Related CN202650547U (en) | 2012-05-23 | 2012-05-23 | Register circuit module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202650547U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723113A (en) * | 2012-05-23 | 2012-10-10 | 常州芯奇微电子科技有限公司 | Register circuit module |
-
2012
- 2012-05-23 CN CN 201220233413 patent/CN202650547U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723113A (en) * | 2012-05-23 | 2012-10-10 | 常州芯奇微电子科技有限公司 | Register circuit module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130102 Termination date: 20140523 |