CN113612474A - Anti-jitter high-speed frequency discriminator circuit - Google Patents
Anti-jitter high-speed frequency discriminator circuit Download PDFInfo
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- CN113612474A CN113612474A CN202110836758.9A CN202110836758A CN113612474A CN 113612474 A CN113612474 A CN 113612474A CN 202110836758 A CN202110836758 A CN 202110836758A CN 113612474 A CN113612474 A CN 113612474A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention provides an anti-jitter high-speed frequency discriminator circuit, wherein Q1, Q2, Q3 and Q4 are respectively the positive phase outputs of four D triggers 1, 2, 3 and 4, and Q3B and Q4B are the negative phase outputs of a third D trigger and a fourth D trigger; q3 and Q3B are connected to the two inputs of the first and gate, Q4 and Q4B are connected to the two inputs of the second and gate; the first AND gate outputs an UP signal, and the second AND gate outputs a DOWN signal; two input ends of the first D trigger are respectively connected with input data Din and an oscillation output Do, a first input end of the second D trigger is connected with the oscillation output Do, and a second input end of the second D trigger is connected with the input data Din through a delay module; first input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q1; second input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q2.
Description
Technical Field
The invention relates to a high-frequency analog integrated circuit design technology, in particular to frequency detection applied to a high-frequency phase-locked loop.
Background
A Frequency Detector (Frequency Detector) and a Phase Detector (Phase Detector PD) usually form core devices of analog and digital Phase-locked loop circuits, and are important components in high-speed communication transceiving systems. The method comprises the steps of sensing the edge of an output signal of an oscillating circuit in a phase-locked loop (PLL) feedback system, detecting the time difference between the edge of the output signal of the oscillating circuit and the edge of a reference clock signal to generate a pulse signal, and adjusting the oscillation starting frequency of the oscillating circuit through the width of the pulse signal to enable the oscillation starting frequency of the oscillating circuit to be the same as a certain multiple of the reference clock frequency. Thereby realizing the frequency and phase locking of the phase-locked loop circuit. The overall circuit diagram is shown in fig. 1, the input signal of the frequency discriminator is input data or a reference clock signal Din and an output signal Do of the voltage-controlled oscillation circuit, the rising edge time difference between the Din and Do signals is converted into a pulse signal through the frequency discriminator, the signal controls the charge pump to realize the output and the inflow of charges, the voltage/current conversion is realized, and the pulse signal is filtered and subjected to noise reduction through a low-pass filter to serve as a control signal of the voltage-controlled oscillation circuit to adjust the frequency and the phase of the Do. In a high-speed (20Gbps) clock and data recovery circuit, when the input data Din contains large jitter, detection errors of the discriminator are caused, and thus frequency locking cannot be achieved.
Disclosure of Invention
The invention provides an anti-jitter high-speed frequency discriminator circuit, which solves the problem that the frequency discriminator cannot carry out frequency locking because the input data Din contains larger jitter.
In order to solve the technical problem, the invention provides an anti-jitter high-speed frequency discriminator circuit which comprises four D triggers, a delay circuit and 2 AND gates;
q1, Q2, Q3 and Q4 are positive phase outputs of four D flip-flops 1, 2, 3 and 4, respectively, and Q3B and Q4B are inverted outputs of a third D flip-flop and a fourth D flip-flop; q3 and Q3B are connected to the two inputs of the first and gate, Q4 and Q4B are connected to the two inputs of the second and gate; the first AND gate outputs an UP signal, and the second AND gate outputs a DOWN signal; two input ends of the first D trigger are respectively connected with input data Din and an oscillation output Do, a first input end of the second D trigger is connected with the oscillation output Do, and a second input end of the second D trigger is connected with the input data Din through a delay module; first input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q1; second input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q2;
when the frequency of the input data Din is higher than the frequency of the oscillation output Do, the UP signal is at a high level, the charge pump provides current for the filter, the output voltage of the filter is increased, and the output frequency of the oscillation circuit is increased; when the frequency of the input data Din is lower than the frequency of the oscillation output Do, the DOWN signal is at a high level, the filter supplies current to the charge pump, the output voltage of the filter is reduced, and the output frequency of the oscillation circuit is reduced.
In a preferred embodiment: the UP signal and the DOWN signal are not always in opposite states.
In a preferred embodiment: when the input data Din contains large jitter, the UP signal and the DOWN signal are simultaneously in a low level state.
Drawings
Fig. 1 is a block diagram of a prior art PLL circuit including a phase detector and a frequency detector;
FIG. 2 is a circuit diagram of an anti-jitter high speed discriminator according to a preferred embodiment of the present invention;
FIG. 3 is a timing diagram of the signals in the preferred embodiment of the present invention, wherein a is a timing diagram of the input data Din with large jitter; b is a timing diagram of input data without large jitter;
fig. 4 is a diagram of simulation results of the preferred embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "top/bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "sleeved/connected," "connected," and the like, are used in a broad sense, and for example, "connected" may be a wall-mounted connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection through an intermediate medium, and a communication between two elements, and those skilled in the art will understand the specific meaning of the terms in the present invention specifically.
Referring to fig. 2, the present embodiment provides an anti-jitter high-speed frequency discriminator circuit, which is composed of four D flip-flops, a delay circuit, and 2 and gates;
q1, Q2, Q3 and Q4 are positive phase outputs of four D flip-flops 1, 2, 3 and 4, respectively, and Q3B and Q4B are inverted outputs of a third D flip-flop and a fourth D flip-flop; q3 and Q3B are connected to the two inputs of the first and gate, Q4 and Q4B are connected to the two inputs of the second and gate; the first AND gate outputs an UP signal, and the second AND gate outputs a DOWN signal; two input ends of the first D trigger are respectively connected with input data Din and an oscillation output Do, a first input end of the second D trigger is connected with the oscillation output Do, and a second input end of the second D trigger is connected with the input data Din through a delay module; first input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q1; second input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q2;
when the frequency of the input data Din is higher than the frequency of the oscillation output Do, the UP signal is at a high level, the charge pump provides current for the filter, the output voltage of the filter is increased, and the output frequency of the oscillation circuit is increased; when the frequency of the input data Din is lower than the frequency of the oscillation output Do, the DOWN signal is at a high level, the filter supplies current to the charge pump, the output voltage of the filter is reduced, and the output frequency of the oscillation circuit is reduced.
After the above design, taking the frequency of the input data Din higher than the frequency of the oscillation output Do as an example, as shown in fig. 3, when both the rising edge and the falling edge of the input data Din contain large jitter, Q3 and Q4B generate opposite signals to keep both the UP signal and the DOWN signal at low level, so that charging and discharging are not performed, and erroneous determination caused by jitter is avoided. When the rising edge and the falling edge of the input data Din both have small jitter, Q3 and Q4B can perform more definite frequency discrimination, and the UP and DOWN signals operate normally. Fig. 4 shows simulation results of the inventive circuit.
The above description is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any person skilled in the art can make insubstantial changes in the technical scope of the present invention within the technical scope of the present invention, and the actions infringe the protection scope of the present invention are included in the present invention.
Claims (3)
1. A jitter tolerant high speed discriminator circuit, comprising: the circuit consists of four D triggers, a delay circuit and 2 AND gates;
q1, Q2, Q3 and Q4 are positive phase outputs of four D flip-flops 1, 2, 3 and 4, respectively, and Q3B and Q4B are inverted outputs of a third D flip-flop and a fourth D flip-flop; q3 and Q3B are connected to the two inputs of the first and gate, Q4 and Q4B are connected to the two inputs of the second and gate; the first AND gate outputs an UP signal, and the second AND gate outputs a DOWN signal; two input ends of the first D trigger are respectively connected with input data Din and an oscillation output Do, a first input end of the second D trigger is connected with the oscillation output Do, and a second input end of the second D trigger is connected with the input data Din through a delay module; first input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q1; second input ends of the third D flip-flop and the fourth D flip-flop are respectively connected to Q2;
when the frequency of the input data Din is higher than the frequency of the oscillation output Do, the UP signal is at a high level, the charge pump provides current for the filter, the output voltage of the filter is increased, and the output frequency of the oscillation circuit is increased; when the frequency of the input data Din is lower than the frequency of the oscillation output Do, the DOWN signal is at a high level, the filter supplies current to the charge pump, the output voltage of the filter is reduced, and the output frequency of the oscillation circuit is reduced.
2. A jitter tolerant high speed discriminator circuit according to claim 1, wherein: the UP signal and the DOWN signal are not always in opposite states.
3. A jitter tolerant high speed discriminator circuit according to claim 1, wherein: when the input data Din contains large jitter, the UP signal and the DOWN signal are simultaneously in a low level state.
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| CN202110836758.9A CN113612474B (en) | 2021-07-23 | 2021-07-23 | Anti-jitter high-speed frequency discriminator circuit |
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| CN202110836758.9A CN113612474B (en) | 2021-07-23 | 2021-07-23 | Anti-jitter high-speed frequency discriminator circuit |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0091102A1 (en) * | 1982-04-02 | 1983-10-12 | Hitachi, Ltd. | Color signal processing circuit for video tape recorders |
| US5661419A (en) * | 1996-05-23 | 1997-08-26 | Sun Microsystems, Inc. | Dynamic phase-frequency detector circuit |
| WO2001067611A1 (en) * | 2000-03-06 | 2001-09-13 | Siemens Aktiengesellschaft | Clock and data regenerator for different data rates |
| KR20020008449A (en) * | 2000-07-20 | 2002-01-31 | 박종섭 | Phase locked loop for improving jitter characteristics |
| DE102004009116B3 (en) * | 2004-02-25 | 2005-04-28 | Infineon Technologies Ag | Delta-sigma frequency discriminator includes dither circuit for altering clock period of reference clock signal used for sampling register for suppression of modulation interference tones |
| WO2008084094A1 (en) * | 2007-01-12 | 2008-07-17 | Texas Instruments Deutschland Gmbh | Phase-locked loop circuit |
| US20090195271A1 (en) * | 2008-02-06 | 2009-08-06 | Boomer James B | Frequency mode selection discriminator and low pass filter |
| CN103187971A (en) * | 2013-02-03 | 2013-07-03 | 南京邮电大学 | Lock detection circuit for charge pump phase locked loop frequency synthesizer |
| US9584303B1 (en) * | 2015-10-28 | 2017-02-28 | Futurewei Technologies, Inc. | Reference-less frequency detector with high jitter tolerance |
| CN109639271A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | Lock the phaselocked loop of indicating circuit and its composition |
| CN109921787A (en) * | 2019-02-27 | 2019-06-21 | 东南大学 | A kind of phase frequency detector of width capture range |
-
2021
- 2021-07-23 CN CN202110836758.9A patent/CN113612474B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0091102A1 (en) * | 1982-04-02 | 1983-10-12 | Hitachi, Ltd. | Color signal processing circuit for video tape recorders |
| US5661419A (en) * | 1996-05-23 | 1997-08-26 | Sun Microsystems, Inc. | Dynamic phase-frequency detector circuit |
| WO2001067611A1 (en) * | 2000-03-06 | 2001-09-13 | Siemens Aktiengesellschaft | Clock and data regenerator for different data rates |
| KR20020008449A (en) * | 2000-07-20 | 2002-01-31 | 박종섭 | Phase locked loop for improving jitter characteristics |
| DE102004009116B3 (en) * | 2004-02-25 | 2005-04-28 | Infineon Technologies Ag | Delta-sigma frequency discriminator includes dither circuit for altering clock period of reference clock signal used for sampling register for suppression of modulation interference tones |
| WO2008084094A1 (en) * | 2007-01-12 | 2008-07-17 | Texas Instruments Deutschland Gmbh | Phase-locked loop circuit |
| US20090195271A1 (en) * | 2008-02-06 | 2009-08-06 | Boomer James B | Frequency mode selection discriminator and low pass filter |
| CN103187971A (en) * | 2013-02-03 | 2013-07-03 | 南京邮电大学 | Lock detection circuit for charge pump phase locked loop frequency synthesizer |
| US9584303B1 (en) * | 2015-10-28 | 2017-02-28 | Futurewei Technologies, Inc. | Reference-less frequency detector with high jitter tolerance |
| CN109639271A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | Lock the phaselocked loop of indicating circuit and its composition |
| CN109921787A (en) * | 2019-02-27 | 2019-06-21 | 东南大学 | A kind of phase frequency detector of width capture range |
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Effective date of registration: 20230613 Address after: Room 402-145, No. 56 Chengyi North Street, Software Park Phase III, Torch High tech Zone, Xiamen City, Fujian Province, 361000 Applicant after: Xiamen Xinshili Microelectronics Co.,Ltd. Address before: 361000 unit 505, No. 1702, Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen, Fujian Applicant before: Xiamen XunXin Electronic Technology Co.,Ltd. |
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