CN108318809A - The built-in self-test circuit of frequency jitter - Google Patents
The built-in self-test circuit of frequency jitter Download PDFInfo
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- CN108318809A CN108318809A CN201710029642.8A CN201710029642A CN108318809A CN 108318809 A CN108318809 A CN 108318809A CN 201710029642 A CN201710029642 A CN 201710029642A CN 108318809 A CN108318809 A CN 108318809A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
- G01R31/31709—Jitter measurements; Jitter generators
Abstract
A kind of built-in self-test circuit of frequency jitter, including frequency reception circuit, timing circuit and shake decision circuitry.Frequency reception circuit executes operation (a)：Commencing signal and stop signal are generated according to frequency signal, wherein stop signal falls behind one or more periods of commencing signal.Timing circuit executes operation (b)：The first time differed between detection commencing signal and stop signal.Frequency reception circuit executes operation (a) with operation (b) repeatedly to generate multiple second times respectively with timing circuit.Shake decision circuitry calculates a reference value according to the second time, calculates shake critical value according to a reference value, obtains at least one of the second time extremum, and calculate amount of jitter according to extremum.If amount of jitter is less than shake critical value, shake decision circuitry output passes through signal.
Description
Technical field
The invention relates to a kind of built-in self-test (built-in self test, BIST) circuits, and especially
About a kind of built-in self-test circuit of frequency jitter.
Background technology
Frequency generating circuit, such as phase-locked loop (phase lock loop, PLL) or delay line loop (delay
Line loop, DLL) it is the frequency signal for generating low jitter.Such frequency generating circuit can be applied to a variety of productions
In product, for example, transmission end of sequence (serial) transmission and receiving terminal etc..However, generally examining with frequency generating circuit
Product when, used detecting instrument is only capable of the frequency of detection frequency, and can not detect the shake of frequency.It therefore, if can be
One built-in self-test circuit is set beside frequency generating circuit to detect the shake of frequency, the detection of product will be had very
Big help.
Invention content
The present invention proposes a kind of built-in self-test circuit of frequency jitter, is suitable for frequency signal, with the period.This
Built-in self-test circuit includes frequency reception circuit, timing circuit and shake decision circuitry.Frequency reception circuit receives frequency
Signal simultaneously executes operation (a)：Commencing signal and stop signal are generated according to frequency signal, wherein stop signal falls behind commencing signal
One or more periods.Timing circuit receives commencing signal and stop signal, and executes operation (b)：It detects commencing signal and stops
The first time differed between signal.Frequency reception circuit executes operation (a) with operation (b) repeatedly with production respectively with timing circuit
Raw multiple second times, these second times include above-mentioned first time.Shake decision circuitry is calculated according to the second time
A reference value, and shake critical value is calculated according to a reference value.It shakes decision circuitry and obtains at least one of second time extremely
Value, and amount of jitter is calculated according to extremum.Shake decision circuitry judges whether amount of jitter is less than shake critical value, if amount of jitter
Whether shake critical value is less than, and shake decision circuitry output passes through signal.
In some embodiments, above-mentioned a reference value is being averaged for the second time, and shakes decision circuitry by a reference value
Default value is multiplied by obtain shake critical value.
In some embodiments, an above-mentioned at least extremum includes the maxima and minima in the second time.Shake
Maximum value is subtracted minimum value to obtain amount of jitter by decision circuitry.
In some embodiments, above-mentioned shake decision circuitry calculates the average to obtain benchmark of maxima and minima
Value, and a reference value is multiplied by default value to obtain shake critical value.
In some embodiments, above-mentioned default value is programmable, default value 0.25,0.125,0.0625 with
One of 0.03125.
In some embodiments, shake decision circuitry includes the first buffer, to store maximum value；Second buffer,
To store minimum value；And counting circuit.
In some embodiments, above-mentioned frequency reception circuit includes first to third flip-flop.First flip-flop it is defeated
Enter end and be coupled to high levle voltage, triggering end is coupled to frequency signal.The input terminal of second flip-flop is coupled to the first flip-flop
Positive output end, triggering end is coupled to frequency signal, and positive output end exports commencing signal.The input terminal coupling of third flip-flop
It is connected to the positive output end of the second flip-flop, triggering end is coupled to frequency signal, and positive output end exports stop signal.
In some embodiments, above-mentioned timing circuit includes the first to the second oscillator.The reception of first oscillator starts
Signal is simultaneously driven by commencing signal.Second oscillator receives stop signal and is driven by stop signal, wherein the second oscillation
The frequency of oscillation of device is more than the frequency of oscillation of the first oscillator.
In some embodiments, above-mentioned timing circuit further includes following elements.The input terminal of 4th flip-flop is coupled to
The output end of first oscillator, triggering end are coupled to the output end of the second oscillator.The input terminal of 5th flip-flop is coupled to
The positive output end of four flip-flops, triggering end are coupled to the output end of the second oscillator.The first input end of NAND gate is coupled to
The reversed-phase output of 4th flip-flop, the second input terminal are coupled to the positive output end of the 5th flip-flop.The timing end of timer
It is coupled to fixed voltage, triggering end is coupled to the output end of the second oscillator, and resetting end is coupled to the output end of NAND gate.
In some embodiments, the resetting end of the first above-mentioned flip-flop, the second flip-flop and third flip-flop all couples
To the output end of NAND gate.
Whether the shake that the built-in self-test circuit that the embodiment of the present invention proposes can be used to detect frequency signal meets mark
It is accurate.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Description of the drawings
Fig. 1 is the block diagram that built-in self-test circuit 100 is exemplified according to an implementation.
Fig. 2 and Fig. 3 is the sequence diagram that each signal in Fig. 1 is exemplified according to an implementation.
【Symbol description】
100：Built-in self-test circuit
110：Frequency reception circuit
111~113,124,125：Flip-flop
120：Timing circuit
121、122：Oscillator
126：NAND gate
127：Timer
130：Shake decision circuitry
131、132：Buffer
133：Counting circuit
CLK：Frequency signal
START：Commencing signal
STOP：Stop signal
D：Input terminal
Q：Positive output end
Inverse output terminal
RST：Reset end
OscA、OscB：Oscillator signal
A、B：Signal
RSTN：Reset signal
UP：Timing end
T1：At the first time
T2、T3：Time
T4~T6：Time point
Specific implementation mode
About " first " used herein, " second " ... etc., not refer in particular to the meaning of order or cis-position, only
In order to distinguish the element described with same technique term or operation.In addition, about " coupling " used herein, two are can refer to
Element is either directly or indirectly electrically connected.That is, when " the first object is coupled to the second object " is described below, the
Other objects can be also set between an object and the second object.
Fig. 1 is the side that built-in self-test (built-in self test, BIST) circuit 100 is exemplified according to an implementation
Block diagram, built-in self-test circuit 100 are whether the shake detected in frequency signal CLK meets a standard, such as sentence
Whether the amount of jitter of disconnected frequency signal CLK is less than 3% etc..Frequency signal CLK is to come from any frequency generating circuit appropriate, example
Such as it is phase-locked loop, delay line loop, oscillator, but the present invention is not intended to limit the source of frequency signal CLK.It is built-in self to survey
Examination circuit 100 includes frequency reception circuit 110, timing circuit 120 and shake decision circuitry 130.
Frequency reception circuit 110 is to receives frequency signal CLK and executes operation (a)：It is opened according to frequency signal CLK generations
Beginning signal START and stop signal STOP.Stop signal STOP falls behind commencing signal START a cycles, this period meaning
It is the period of frequency signal CLK.Significantly, since the reason of shake, the period of frequency signal CLK may be at any time
Change, but this has no effect on the running of frequency reception circuit 110.Specifically, frequency reception circuit 110 includes the first flip-flop
111, the second flip-flop 112 and third flip-flop 113.The input terminal D of first flip-flop 111 is coupled to high levle voltage and (patrols
Collect " 1 "), triggering end (being also known as frequency end) is coupled to frequency signal CLK.The input terminal D of second flip-flop 112 is coupled to first
The positive output end Q of flip-flop 111, triggering end is coupled to frequency signal CLK, and positive output end Q exports commencing signal
START.The input terminal D of third flip-flop 113 is coupled to the positive output end Q of the second flip-flop 112, and triggering end is coupled to frequency
Signal CLK, and positive output end Q output stop signals STOP.Referring to Fig. 1 and Fig. 2, frequency signal CLK forms first
When a rising edge, the positive output end Q output high levles of the first flip-flop 111, and the second flip-flop 112 and third flip-flop
113 positive output end Q exports low level.When frequency signal CLK forms second rising edge, the first flip-flop 111 is just
Phase output terminal Q still exports high levle, but the positive output end Q of the second flip-flop 112 is converted to high levle by low level and (is formed
One rising edge), the positive output end Q of third flip-flop 113 exports low level.Frequency signal CLK forms third and rises
When edge, the positive output end Q of the first flip-flop 111 still exports high levle, and the positive output end Q of the second flip-flop 112 is defeated
Go out high levle, the positive output end Q of third flip-flop 113 is converted to high levle by low level and (forms a rising edge at this time
Edge).Whereby, the rising edge of stop signal STOP can fall behind the rising edge a cycle of commencing signal START.
Timing circuit 120 can receive commencing signal START and stop signal STOP, and execute operation (b)：Detection starts letter
Number first time T1 differed between START and stop signal STOP.That is, timing circuit 120 is to calculate one
The time span in period.In this embodiment, in timing circuit 120 include time-to-digit converter based on cursor
(Vernier-based time to digital converter).Specifically, timing circuit 120 includes the first oscillation
Device 121, the second oscillator 122, the 4th flip-flop 124, the 5th flip-flop 125, NAND gate 126 and timer 127.First oscillation
122 for example, ring-like (ring) oscillator of device 121 and the second oscillator, but inductance capacitance can also be used in other embodiments
(LC) oscillator or other suitable oscillators, the present invention are simultaneously not subject to the limits.First oscillator 121 receives commencing signal START
And it is driven with outputting oscillation signal OscA by the rising edge of commencing signal START.Second oscillator 122 receives stop signal
STOP is simultaneously driven by the rising edge of stop signal STOP with outputting oscillation signal OscB.Wherein the second oscillator 122 shakes
Swing the frequency of oscillation that frequency is more than the first oscillator 121, for example, the second oscillator 122 frequency of oscillation more 1%~8%, but
The present invention is simultaneously not subject to the limits.The input terminal D of 4th flip-flop 124 is coupled to the output end of the first oscillator 121 to receive oscillation
Signal OscA, triggering end are coupled to the output end of the second oscillator 122 to receive oscillator signal OscB, and positive output end Q is then defeated
Go out signal B.The input terminal D of 5th flip-flop 125 is coupled to the positive output end Q of the 4th flip-flop 124, and triggering end is coupled to
The output end of two oscillators 122 is to receive oscillator signal OscB, positive output end Q then output signal A.The first of NAND gate 126
Input terminal is coupled to the reversed-phase output of the 4th flip-flop 124The positive that second input terminal is coupled to the 5th flip-flop 125 is defeated
Outlet Q is to receive signal A, and NAND gate 126 exports reset signal RSTN.The timing end UP of timer 127 is coupled to one
Fixed voltage (being, for example, high levle), triggering end is coupled to the output end of the second oscillator 122 to receive oscillator signal OscB, again
It sets end RST and is coupled to the output end of NAND gate 126 to receive reset signal RSTN.
The operation principles of timing circuit 120 are as follows, referring to Fig. 1 and Fig. 2.First oscillator 121 is in commencing signal
START starts to shake when forming rising edge, and the second oscillator 122 starts to shake when end signal STOP forms rising edge
It swings, therefore can fall behind oscillator signal OscA in starting stage oscillator signal OscB.However, due to the oscillation frequency of oscillator signal OscB
Rate is larger, i.e. the period is smaller, therefore oscillator signal OscB can gradual " catching up with " oscillator signal OscA.As an example it is assumed that oscillation
It is equal to time T after the period that the period of signal OscA subtracts oscillator signal OscBΔ.In fig. 2, first of oscillator signal OscA
Time T2 is differed between rising edge and first rising edge of oscillator signal OscB, on second of oscillator signal OscA
It rises and has differed time T3 between edge and second rising edge of oscillator signal OscB, time T2 can be more than time T3, and (this is poor
Away from usual very little, fail to clearly identify in diagram), it is explicitly T2=T3+TΔ.Therefore, oscillator signal OscB
Rising edge can move closer to the rising edge of oscillator signal OscA.Assuming that after have passed through N number of period (N is positive integer), shake
The rising edge of oscillator signal OscA can be synchronized with by swinging the rising edge of signal OscB, this expression can be according to following equation sequence (1)
To calculate first time T1.
T1=NTΔ…(1)
Timer 127 is to calculate above-mentioned positive integer N, and the fortune of the 4th flip-flop 124 and the 5th flip-flop 125
Work is equal to a phase detectors, whether is synchronized with oscillator signal OscB to detection oscillator signal OscA.Specifically, it asks
Referring to Fig.1 with Fig. 3, during oscillator signal OscB chases oscillator signal OscA, the rising edge meeting of oscillator signal OscB
Triggering timing device 127, since the voltage on the UP of timing end is fixed value, the constantly cumulative numerical value of the meeting of timer 127, this number
Value is equal to the number of frequency in oscillator signal OscB.In time point T4, when the 4th flip-flop 124 is according to oscillator signal OscB's
Rising edge can be sampled to high levle when sampling oscillator signal OscA, this indicates that oscillator signal OscB does not catch up with oscillator signal also
Signal B on OscA, the positive output end Q of the 4th flip-flop 124 can be high levle.In time point T5, when the 4th flip-flop 124
Low level can be sampled to when sampling oscillator signal OscA according to the rising edge of oscillator signal OscB, this indicates oscillator signal
OscB has caught up with oscillator signal OscA, and signal B can be converted to low level from high levle, and signal A can be equal to a frequency
The signal B (i.e. high levle) of rate.In time point T6, the first input end of NAND gate 126 is reverse phase in signal B, is high levle,
And the second input terminal of NAND gate 126 be signal A and high levle, therefore NAND gate 126 export reset signal RSTN meetings
Low level is converted to from high levle, timer 127 can be reset, and timer 127 can remain added up numerical value
As above-mentioned positive integer N.As shown in aforesaid equation (1), this positive integer N can be used to calculate first time T1.
On the other hand, the resetting end RST of the first flip-flop 111, the second flip-flop 112 and third flip-flop 113 can coupling
The output end of NAND gate 126 is connected to receive reset signal RSTN, therefore can all be weighed in time point T6 flip-flop 111~113
It sets.Next, frequency reception circuit 110 can regenerate commencing signal START and stop signal STOP, that is, re-execute above-mentioned
Operation (a), and timing circuit 120 can calculate primary first time T1 again again, that is, re-execute above-mentioned operation (b).Frequently
Rate receiving circuit 110 and timing circuit 120 can execute operation (a) and operate (b) multiple (such as 8 times, but the present invention is not respectively
Limit herein) to generate multiple second times, these second times just include first time T1.Each second time indicates
Period of frequency signal CLK, but since frequency signal CLK may have shake, this indicates that these second times may not phase each other
Together, next shake decision circuitry 130 can judge whether the degree of shake meets a mark according to these second times
It is accurate.
Shake decision circuitry 130 includes the first buffer 131, the second buffer 132 and counting circuit 133.Whenever production
When the raw second new time, as long as this second time is more than the numerical value in the first buffer 131, first can be kept in
Numerical value in device 131 replaces with the second new time；As long as the second new time is less than the numerical value in the second buffer 132, just
Numerical value in second buffer 132 can be replaced with to the second new time.Thus, which the first buffer 131 can be used to deposit
Maximum value is stored up, and the second buffer 132 can be used to store minimum value.Counting circuit 133 can calculate the flat of maxima and minima
As an a reference value, to be represented by following equation sequence (2), be worth on the basis of wherein Base, Max is maximum value, and Min is most
Small value.
Base=(Max+Min/2 ... (2)
On the other hand, a reference value can be multiplied by a default value to obtain shake critical value by counting circuit 133.Present count
Value is programmable, one of for example, 0.25,0.125,0.0625 and 0.03125, take these numerical value be because
As long as the position for displacement 2,3,4 or 5 that a reference value turns right when doing the operation being multiplied.However, in other embodiments, it is above-mentioned
Other numerical value can also be used in default value, and the present invention is simultaneously not subject to the limits.The calculating such as following equation sequence (3) of critical value is shaken,
Middle jitterspcTo shake critical value, S is default value.
jitterspc=Base × S ... (3)
In addition, maximum value can be subtracted minimum value as amount of jitter, to be represented by following equation sequence by counting circuit 133
(4), wherein jitter is amount of jitter.
Jitter=Max-Min ... (4)
Counting circuit 130 can judge whether amount of jitter jitter is less than shake critical value jitterspcIf amount of jitter
Jitter is less than shake critical value jitterspc, then shaking decision circuitry 130 can export through signal, indicate frequency signal CLK
The detection of shake is passed through.For example, it if user wants whether detection amount of jitter is less than 12.5%, can select pre-
If numerical value is 0.125, the calculated shake critical value jitter of institutespcCan be theoretically the 12.5% of the period, if amount of jitter
Jitter is less than shake critical value jitterspc, that is, indicate to pass through detection.
Significantly, since shake critical value jitterspcWith amount of jitter jitter counted according to the second time
It calculates, therefore can be to avoid the influence of processing procedure voltage temperature (process voltage temperature, PVT).Citing comes
Say, if because of temperature rise or decline so that the frequency shift of the first oscillator 121, the second oscillator 122, then because
Amount of jitter jitter and shake critical value jitterspcThe change that can be synchronized, therefore the judgement of shake is not influenced.
In the above-described embodiment, stop signal STOP is backward commencing signal START a cycles, but in other implementations
Stop signal STOP can also fall behind commencing signal START more a periods in example, and such embodiment has no effect on sentencing for shake
It is disconnected.
In the above-described embodiment, a reference value is averagely getting for calculating maxima and minima, but in other implementations
A reference value is alternatively being averaged for the second time in example.Such as there are one mnemon (not shown) for tool in shake decision circuitry 130
It stores these the second times, and has another computing unit (not shown) to calculate being averaged for these the second times, it is real herein
It applies in example, a reference value can equally be multiplied by default value to obtain shake critical value.In other embodiments, a reference value is alternatively
The median of two times, the present invention are simultaneously not subject to the limits.On the other hand, amount of jitter is to subtract maximum value in the above-described embodiment
Minimum value and obtain, but in other embodiments can also be by an extremum (can be maximum value or minimum value) and a reference value
Subtract each other and calculates amount of jitter.
In other words, shake decision circuitry 130 can calculate an a reference value according to the second time, and according to this reference value meter
A shake critical value is calculated, this reference value can be average value, median or maxima and minima in the second time
It is average.Shake decision circuitry 130 can also obtain at least one of the second time extremum, this extremum can be minimum value and/
Or minimum value, and amount of jitter is calculated according to this extremum, such as maximum value is subtracted into minimum value, or maximum value is subtracted
A reference value, or a reference value is subtracted into minimum value.Since shake critical value and amount of jitter were calculated according to the second time
Go out, therefore can be influenced to avoid PVT, those skilled in the art when can according to it is such teaching come design other a reference values with
Amount of jitter, the present invention is not limited to the above embodiments.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any people in the art
Member, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus protection scope of the present invention when with
Subject to the range of appended claims protection.
Claims (10)
1. a kind of built-in self-test circuit of frequency jitter is suitable for frequency signal, the frequency signal has the period, described
Built-in self-test circuit includes：
Frequency reception circuit receives the frequency signal and executes operation (a)：According to the frequency signal generate commencing signal with
Stop signal, wherein the stop signal falls behind described one or more described periods of commencing signal；
Timing circuit receives the commencing signal and the stop signal and executes operation (b)：Detect the commencing signal and institute
The first time differed between stop signal is stated,
The wherein described frequency reception circuit and the timing circuit execute the operation (a) and the operation (b) respectively repeatedly with
Multiple second times are generated, the multiple second time includes the first time；And
Decision circuitry is shaken, to calculate a reference value according to the multiple second time, and is calculated according to a reference value
Critical value is shaken,
The wherein described shake decision circuitry obtains at least extremum in the multiple second time, and according to described at least one
Extremum calculates amount of jitter,
The wherein described shake decision circuitry judges whether the amount of jitter is less than the shake critical value,
Wherein if the amount of jitter is less than the shake critical value, the shake decision circuitry output passes through signal.
2. built-in self-test circuit as described in claim 1, wherein a reference value is the flat of the multiple second time
, and a reference value is multiplied by default value to obtain the shake critical value by the shake decision circuitry.
3. built-in self-test circuit as described in claim 1, wherein an at least extremum includes the multiple second
The maximum value is subtracted the minimum value to obtain described tremble by the maxima and minima in the time, the shake decision circuitry
Momentum.
4. built-in self-test circuit as claimed in claim 3, wherein the shake decision circuitry calculate the maximum value with
The minimum value is averaged to obtain a reference value, and a reference value is multiplied by default value and is faced with obtaining the shake
Dividing value.
5. built-in self-test circuit as claimed in claim 4, wherein the default value is programmable, the present count
Value is one of 0.25,0.125,0.0625 and 0.03125.
6. built-in self-test circuit as claimed in claim 4, wherein the shake decision circuitry includes：
First buffer, to store the maximum value；
Second buffer, to store the minimum value；And
Counting circuit.
7. built-in self-test circuit as described in claim 1, wherein the frequency reception circuit includes：
First flip-flop, input terminal are coupled to high levle voltage, and triggering end is coupled to the frequency signal；
Second flip-flop, input terminal are coupled to the positive output end of first flip-flop, and triggering end is coupled to the frequency
The positive output end of signal, second flip-flop exports the commencing signal；And
Third flip-flop, input terminal are coupled to the positive output end of second flip-flop, and triggering end is coupled to described
The positive output end of frequency signal, the third flip-flop exports the stop signal.
8. built-in self-test circuit as claimed in claim 7, wherein the timing circuit includes：
First oscillator receives the commencing signal and is driven by the commencing signal；And
Second oscillator receives the stop signal and is driven by the stop signal, wherein second oscillator shakes
Swing the frequency of oscillation that frequency is more than first oscillator.
9. built-in self-test circuit as claimed in claim 8, wherein the timing circuit further includes：
4th flip-flop, input terminal are coupled to the output end of first oscillator, and triggering end is coupled to second oscillation
The output end of device；
5th flip-flop, input terminal are coupled to the positive output end of the 4th flip-flop, and triggering end is coupled to described second
The output end of oscillator；
NAND gate, first input end are coupled to the reversed-phase output of the 4th flip-flop, and the second input terminal is coupled to described
The positive output end of 5th flip-flop；And
Timer, timing end are coupled to fixed voltage, and triggering end is coupled to the output end of second oscillator, resetting
End is coupled to the output end of the NAND gate.
10. built-in self-test circuit as claimed in claim 9, wherein first flip-flop, second flip-flop with
The resetting end of the third flip-flop is coupled to the output end of the NAND gate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113000416A (en) * | 2021-02-05 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Test screening method of oscillator circuit module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113000416A (en) * | 2021-02-05 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Test screening method of oscillator circuit module |
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