JPH10173520A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a PLL circuit from getting into a deadlock state and to make it possible to return into a normal rock state by detecting the phase difference between a reference signal and a feedback signal and discharging an error signal or control signal under the control of a reset signal. SOLUTION: A phase comparator 12 detects the phase difference between the external reference signal of specific frequency and a feedback signal from a voltage-controlled oscillator 18 and outputs a control signal UP or DOWN. A charge pump 14 outputs an error signal corresponding to the phase difference according to the control signal from the phase comparators 12 when the reset signal is inactive. Here, the reset signal becomes active when a PLL circuit 10 possibly comes to a deadlock or has come to the deadlock. At this time, the charge pump 14 outputs the error signal which lowers the voltage level of the control signal irrelevantly to the control signal. Then the output signal and feedback signal are outputted from the voltage-controlled oscillator 18 through a loop filter 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (PLL) circuit for generating an output signal phase-locked to a reference signal.
Loop: phase-locked loop).

[0002]

2. Description of the Related Art FIG. 4 is a conceptual diagram of an example of a conventional PLL circuit. The illustrated PLL circuit 30 includes a phase comparator 32 that detects a phase difference between the reference signal and the feedback signal and outputs a control signal, a charge pump 34 that outputs an error signal having a pulse width corresponding to the control signal, Based on the control of the loop filter 36 that outputs a control signal of a voltage level corresponding to the error signal and the enable signal,
It has a voltage controlled oscillator 38 that outputs a feedback signal and an output signal of an oscillation frequency according to the voltage level of the control signal.

In this PLL circuit 30, a charge pump 34 includes a P-type MOS transistor (hereinafter referred to as a PMOS transistor).
40) and an N-type MOS transistor (hereinafter referred to as N
And a control signal UP, DOWN output from the phase comparator 32 at its gate.
Is entered. In addition, a PMOS 40 and an NMOS
The source of the charge pump 3 is connected to the power supply and the ground, and the drain thereof is short-circuited.
4 as an error signal.

Here, the enable signal is a signal provided to stop the oscillation of the voltage controlled oscillator 38 during standby, for example, to reduce power consumption.
In the following example, the voltage-controlled oscillator 38 oscillates at an oscillation frequency corresponding to the voltage level of the control signal when the enable signal is set to a high level, and stops the oscillation when the enable signal is set to a low level. A low level is output as the feedback signal and the output signal.

In the PLL circuit 30, a phase difference between a reference signal and a feedback signal is detected by a phase comparator 32, and a control signal is output. An error signal having a pulse width corresponding to the control signal is generated by the charge pump 34. The error signal is converted into an analog signal by a loop filter 36, and then input to a voltage controlled oscillator 38 as a control signal. Thereby, the oscillation frequency of the feedback signal is changed according to the voltage level of the control signal.

For example, when the phase of the feedback signal is later than that of the reference signal, the voltage level of the control signal is increased in order to advance the phase of the feedback signal, and conversely, the voltage level is decreased when it is earlier. Then, similarly, by repeatedly detecting the phase difference between the reference signal and the feedback signal whose oscillation frequency has been changed, the frequency and phase of the reference signal and the feedback signal are synchronized (locked) to obtain an output signal. ing.

As described above, in the PLL circuit 30,
The frequency and phase of the feedback signal are controlled according to the voltage level of the control signal, and an output signal in which the phase of the reference signal and the phase of the feedback signal are synchronized is obtained.

Incidentally, the PLL circuit 30 is not only formed as an IC as a single unit, but also mounted on an individual IC such as a control device, a processing device, a CPU, or the like, and formed as an on-chip. In some cases, it is used for such purposes. In this case, considering various conditions such as voltage fluctuations, temperature fluctuations, and process fluctuations, the voltage controlled oscillator 38 has a sufficient margin so that it can operate from a low frequency to a high frequency around the oscillation frequency to be used. It is necessary to design.

As described above, in an IC mounted with the PLL circuit 30 designed with a sufficient margin for the oscillation frequency of the voltage controlled oscillator 38, the operating frequency is very much higher than the actual operating frequency when the IC is actually operated. The voltage controlled oscillator 38 can be oscillated to a high frequency. For example, in the worst condition, even if the oscillation does not reach a very high frequency, the maximum oscillation frequency of the voltage controlled oscillator 38 becomes a very high frequency in the typical condition and further in the best condition.

[0010] Circuit elements such as logic gates and flip-flops are usually connected to the path of the feedback signal.
When the operation of the LL circuit 30 is unstable, when the voltage level of the control signal increases and the oscillation frequency of the voltage controlled oscillator 38 increases, any circuit element on the path of the feedback signal causes the oscillation of the voltage controlled oscillator 38 to increase. In some cases, it becomes impossible to toggle at the frequency, and the feedback signal is not input to the phase comparator 32.

As shown in an example of the operation of the PLL circuit 30 in the timing chart of FIG. 5, for example, the reference signal is oscillated and is input to the phase comparator 32 for reasons such as reduction of power consumption. In this state, even when the enable signal is set to low level and the operation of the voltage controlled oscillator 38 is stopped, the feedback signal is fixed at low level, and the feedback signal of the oscillation frequency corresponding to the control signal is output to the phase comparator 32. Will not be entered.

When the feedback signal is no longer input to the phase comparator 32, the phase comparator 32 determines that the feedback signal is later than the reference signal, and further performs control for increasing the oscillation frequency of the voltage controlled oscillator 38. Output a signal. Thus, the voltage level of the control signal is further increased, and is finally fixed at a high voltage level. Thereafter, if the path of the feedback signal is a circuit that does not operate at a high frequency, a deadlock state occurs in which the feedback signal does not toggle even if the operation of the voltage controlled oscillator 38 is restarted.

However, once the PLL circuit 30 has fallen into a deadlock state, it cannot be returned to a normal locked state unless initialization such as turning off the power is performed. Was difficult to construct.

Therefore, in order to avoid a deadlock state in an IC on which the PLL circuit 30 is mounted,
In order to operate up to a frequency much higher than the actual operating frequency of the IC, the design must be made in consideration of the upper limit operation frequency of the feedback signal path. In particular, PL
When the L circuit 30 is used for clock control, it is necessary to enable the clock signal path to operate at a frequency much higher than the actual operating frequency, and the load on the clock signal path becomes severely restricted. However, there are problems in that the design restrictions are increased and the design becomes very difficult.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a deadlock state from occurring in view of the above-mentioned problems in the prior art. It is an object of the present invention to provide a PLL circuit that can return to a normal locked state even if there is any.

[0016]

To achieve the above object, the present invention provides a phase comparator for detecting a phase difference between a reference signal and a feedback signal and outputting a control signal; A charge pump for outputting an error signal having a pulse width corresponding to a phase difference between the reference signal and the feedback signal, and a loop for outputting a control signal having a voltage level corresponding to the pulse width of the error signal. A filter, a voltage-controlled oscillator that outputs the feedback signal having an oscillation frequency corresponding to a voltage level of the control signal, and a discharge circuit that discharges at least one of the error signal or the control signal by controlling a reset signal. A PLL circuit is provided.

Here, it is preferable that the discharge circuit discharges the error signal while stopping charge-up of the error signal by the charge pump.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings. FIG. 1 is a conceptual diagram of one embodiment of a PLL circuit according to the present invention. The PLL circuit 10 of the present invention basically generates an output signal phase-locked to a reference signal. In the illustrated example, the PLL circuit 10 includes a phase comparator 12, a charge pump 14, a loop filter 16, and a voltage-controlled oscillator 18. Have.

In the illustrated PLL circuit 10, the phase comparator 12 determines a phase between a reference signal of a predetermined frequency supplied from outside the PLL circuit 10 and a feedback signal supplied from a voltage controlled oscillator 18 described later. It detects a phase difference and outputs control signals UP and DOWN as a result of the phase comparison.

Subsequently, the charge pump 14 basically operates according to a control signal supplied from the phase comparator 12 when a later-described reset signal is in an inactive state.
It outputs an error signal having a pulse width corresponding to the phase difference between the reference signal and the feedback signal. In the illustrated example, P-type MOS transistors (hereinafter, referred to as PMOS) 20, 22 and N-type MOS It has transistors (hereinafter, referred to as NMOS) 24 and 26.

In the illustrated charge pump 14, the PMOS 20 and the NMOS 26 are replaced by the PL of the present invention.
The L circuit 10 constitutes an example of a discharge circuit. The discharge circuit discharges at least one of the error signal and the control signal, and may be configured to be included in the charge pump 14, or may be entirely configured as in a PLL circuit 44 in FIG. You may comprise independently.

Here, the PMOS 20 and the NMOS 26
Sources are connected to power and ground, respectively.
A reset signal is input to the gate. PMO
The sources of S22 and NMOS 24 are respectively PMO
The control signals UP and DOWN output from the phase comparator 12 are input to the gate and the drain of S20, respectively.
The charge pump 14 is short-circuited to the drain of S26.
Are output as error signals.

The above-mentioned reset signal is supplied to the PLL circuit 10
Is a signal supplied when there is a possibility of falling into a deadlock state or when a deadlock state actually occurs. When the reset signal is made active, that is, in the illustrated example, the active state is at a high level. , The charge pump 14 outputs control signals UP, DO
Regardless of WN, an error signal that lowers the voltage level of the control signal, in the illustrated example, a low-level error signal is output.

In the illustrated example, a signal obtained by inverting an enable signal described later by the inverter 28 is used as the reset signal. However, the present invention is not limited to this.
For example, a reset signal may be supplied independently. Further, the reset signal may be supplied from outside the PLL circuit 10, or the PLL circuit 10 may enter a deadlock state inside the PLL circuit 10, or
A circuit for detecting the fall may be provided, and a detection signal from this circuit may be used as a reset signal.

Subsequently, the loop filter 16 converts the error signal supplied from the charge pump 14 into an analog signal, and outputs a control signal having a voltage level corresponding to the error signal. The voltage controlled oscillator 18
Basically, when the enable signal is in the active state, it outputs a feedback signal and an output signal having an oscillation frequency corresponding to the voltage level of the control signal supplied from the loop filter 16.

The above-mentioned enable signal is, for example, a signal supplied from the outside of the PLL circuit 10 in order to stop the oscillation of the voltage controlled oscillator 18 during standby and reduce the power consumption. Here, when the enable signal is in an inactive state, for example, a low level of the inactive state, the oscillation is stopped regardless of the voltage level of the control signal, and a low level is output as a feedback signal and an output signal. And

In the PLL circuit 10 of the present invention, the voltage-controlled oscillator 18 may or may not be provided with an enable signal. When an enable signal is not provided to the voltage-controlled oscillator 18, for example, in the illustrated PLL circuit 10, as described above,
A reset signal may be directly supplied from outside the L circuit 10 or a deadlock detection signal generated internally may be used. The PLL circuit 10 of the present invention is basically configured as described above.

Next, the operation of the PLL circuit 10 of the present invention will be described. First, an operation in a case where the PLL circuit 10 enters a normal lock state without falling into a deadlock state will be described.

In the illustrated PLL circuit 10, the enable signal is set to the high level in the active state, that is, the reset signal is set to the low level in the inactive state, and the charge pump 14 controls the control signals UP and DOWN.
When the voltage control oscillator 18 is set to operate according to the control signal, first, the phase difference between the reference signal and the feedback signal is detected by the phase comparator 12, and the phase difference is detected. The resulting control signal U
P and DOWN are output.

For example, in the phase comparator 12, when the phase of the feedback signal is later than the phase of the reference signal,
While the control signal DOWN is held at the low level, the control signal UP is set to the low level for a predetermined time according to the phase difference between the two. On the other hand, when the phase of the feedback signal is earlier than the phase of the reference signal, the control signal DOWN is kept at the high level, and the control signal DOWN is kept at the high level for a predetermined time according to the phase difference between the two.

The control signal U output from the phase comparator 12
P and DOWN are input to the charge pump 14, and the charge pump 14 outputs an error signal having a pulse width corresponding to a phase difference between the reference signal and the feedback signal. Here, in the charge pump 14, since the reset signal is at the low level of the inactive state, the PMOS 20 is turned on and the PMOS 20 is turned on.
26 is in an off state.

Therefore, when the control signal UP is set to the low level while the control signal DOWN is maintained at the low level,
The PMOS 22 is turned on, and the NMOS 24 is turned off.
Is charged up for a predetermined period of time according to the pulse width of the control signal UP, and from the charge pump 14,
A high-level error signal having a pulse width corresponding to the phase difference between the reference signal and the feedback signal is output.

Conversely, when the control signal DOWN is set to the high level while the control signal UP is held at the high level, the PMOS 22 is turned off, the NMOS 24 is turned on, and the error signal is turned on. NMOS 24
Is discharged for a predetermined period of time according to the pulse width of the control signal DOWN, and a low-level error signal having a pulse width corresponding to the phase difference between the reference signal and the feedback signal is output from the charge pump 14. Is output.

The error signal output from the charge pump 14 is input to the loop filter 16 and the loop filter 1
6, the control signal is converted into an analog signal in accordance with the filter constant, and a control signal having a predetermined voltage level is output. The control signal output from the loop filter 16 is input to the voltage controlled oscillator 18, and the oscillation frequency of the feedback signal and the output signal output from the voltage controlled oscillator 18 is changed according to the voltage level of the control signal.

Then, similarly, the frequency and phase of the reference signal and the output signal are synchronized (locked) by repeatedly comparing the reference signal with the feedback signal whose oscillation frequency has been changed. PLL circuit 10 of the present invention
Basically works as described above.

Next, for example, in order to stop the oscillation of the voltage controlled oscillator 18 at the time of standby and reduce the power consumption, the enable signal is set to the inactive state at the low level, and then to the active state at the high level again. The operation in such a case will be described with reference to the timing chart shown in FIG.

After the frequency and phase of the reference signal and the output signal are synchronized in the PLL circuit 10 as described above, as shown in the timing chart of FIG.
When the enable signal is set to a low level, which is an inactive state, with the reference signal oscillating and being input to the phase comparator 32, the feedback signal output from the voltage controlled oscillator 18 first becomes Regardless of the voltage level, the oscillation is stopped and the level becomes low.

In the phase comparator 12, when the oscillation of the feedback signal is stopped and the level is set to the low level while the reference signal is still oscillated, as described in the description of the prior art, the phase comparator 12 has a higher level than the reference signal. It is determined that the phase of the feedback signal is later than the control signal DOWN.
Is maintained at the low level, the control signal UP is set to the low level for a predetermined time according to the phase difference between them, and the PMOS2
2 is turned on, and the NMOS 24 is turned off.

However, in the illustrated PLL circuit 10, when the enable signal is set to the low level, the reset signal is set to the active high level via the inverter 28, and the charge pump 14
20 is turned off, and NMOS 26 is turned on. Therefore, the charge-up of the error signal is stopped by the PMOS 20, and the error signal is discharged by the NMOS 26, and is set to the low level regardless of the control signals UP and DOWN.

Here, in the charge pump 14 in the illustrated example, the PMOS 20 is turned off by the reset signal, so that the error signal can be prevented from being charged up by the paths of the PMOSs 20 and 22.
The occurrence of leakage current due to the paths of the PMOS 20, 22 and the NMOS 26 is prevented. Therefore, as in the case where the enable signal is deactivated, the PLL
There is an advantage that power consumption when the operation of the circuit 10 is stopped can be reduced.

Subsequently, the low-level error signal output from the charge pump 14 is converted by the loop filter 16 into an analog signal corresponding to the filter constant, and the voltage level of the control signal is reduced. Therefore, in the PLL circuit 10 of the present invention, even when, for example, the enable signal is deactivated and the oscillation of the feedback signal is stopped, the voltage level of the control signal is reduced by the reset signal. It is possible to prevent the locked state.

After that, when the enable signal is set to the high level in the active state, the reset signal goes to the low level in the inactive state, and the PMOS 20 and the NMOS 26 constituting the charge pump 14 are turned on and off, respectively. Further, since the voltage level of the control signal is lowered, the voltage control oscillator 1
8 outputs a feedback signal and an output signal having an oscillation frequency corresponding to the voltage level of the control signal.

Thereafter, as described above, the reference signal and the feedback signal are repeatedly compared, and finally, the frequency and phase of the reference signal and the output signal are synchronized again.

As described above, in the PLL circuit 10 of the present invention, the voltage level of the control signal can be reduced by setting the reset signal to the active state, so that the PLL circuit 10 falls into a deadlock state. Can be prevented beforehand, and conversely, when the PLL circuit 10 may fall into a deadlock state,
Even when a deadlock state actually occurs, the lock signal can be returned to a normal locked state by setting the reset signal to the active state.

As described above, the PLL circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

For example, FIG. 3 shows a conceptual diagram of another embodiment of the PLL circuit of the present invention. The PLL circuit 44 in the illustrated example includes:
In the PLL circuit 10 shown in FIG. 1, an example in which a discharge circuit is configured independently of a charge pump 14 is shown. Note that the charge pump 34
Since it has the same configuration as the conventional PLL circuit 30 shown in FIG. 4, the same reference numerals are given to the same components in the figure, and the description thereof will be omitted.

In the PLL circuit 44 of the illustrated example, the discharge circuit 46 includes a P
It has an NMOS 48 having a larger transistor size than the MOS 40 and the NMOS 42. And NMOS4
The source of 8 is connected to the ground, the reset signal is input to its gate, and its drain is connected to the error signal.

In the illustrated PLL circuit 44, when the reset signal is set to the active high level, the NMOS 48 of the discharge circuit 46 is turned on, the error signal is discharged, and the control signal is passed through the loop filter 16. Is lowered. Here, when the PMOS 40 and the NMOS 48 are turned on at the same time, the error signal is
The voltage level is in accordance with the on-resistance division ratio of the OS 40 and the NMOS 48.

The voltage level of the error signal is lowered by setting the reset signal to the active state. As a result, the voltage level of the control signal is lowered. PL shown
In the L circuit 44, the drain of the N-type MOS transistor 48 whose source is connected to the ground and whose gate receives the reset signal may be connected to the control signal to directly discharge the voltage level of the control signal.

[0050]

As described in detail above, the P of the present invention
The LL circuit includes a discharge circuit, and discharges at least one of an error signal and a control signal by controlling a reset signal. Therefore, according to the PLL circuit of the present invention, the voltage level of the control signal can be reduced by controlling the reset signal, so that the PLL circuit can be prevented from falling into a deadlock state. Conversely, even when the PLL circuit may fall into a deadlock state or actually falls into a deadlock state, the PLL circuit can be returned to a normal lock state, and a stable PLL circuit system can be obtained. Can be built. Further, by configuring the discharge circuit to stop charging the error signal by the charge pump and discharge the error signal, it is possible to further reduce power consumption.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a timing chart of an embodiment showing an operation of the PLL circuit of the present invention.

FIG. 3 is a conceptual diagram of another embodiment of the PLL circuit of the present invention.

FIG. 4 is a conceptual diagram of an example of a conventional PLL circuit.

FIG. 5 is a timing chart showing an example of the operation of a conventional PLL circuit.

[Explanation of symbols]

10, 30, 44 PLL circuit 12, 32 Phase comparator 14, 34 Charge pump 16, 36 Loop filter 18, 38 Voltage controlled oscillator 20, 22, 40 P-type MOS transistor (PMO
S) 24, 26, 42, 48 N-type MOS transistor (N
MOS) 28 inverter 46 discharge circuit

Claims (2)

[Claims] A phase comparator for detecting a phase difference between a reference signal and a feedback signal and outputting a control signal; and detecting a phase difference between the reference signal and the feedback signal according to the control signal. A charge pump for outputting an error signal having a corresponding pulse width, a loop filter for outputting a control signal having a voltage level corresponding to the pulse width of the error signal, and an oscillation frequency corresponding to the voltage level of the control signal. A PLL circuit comprising: a voltage controlled oscillator that outputs a feedback signal; and a discharge circuit that discharges at least one of the error signal or the control signal by controlling a reset signal. 2. The PLL circuit according to claim 1, wherein the discharge circuit discharges the error signal while stopping charge-up of the error signal by the charge pump.