KR102348057B1 - Device of controlling phase clock for low emi characteristic - Google Patents

Abstract

A clock signal phase control device for reducing electromagnetic interference includes: first and second inverters outputting a first output clock signal having a first phase based on a first input clock signal having a first phase; a third inverter and a fourth inverter outputting a second output clock signal having a second phase based on a second input clock signal having a second phase; a first variable inverter passing the first input clock signal to generate a third output clock signal; a second variable inverter for transferring the second input clock signal to generate the third output clock signal; a first transmission gate connected to an output terminal of the second variable inverter and configured to change a path of an output signal of the second variable inverter according to an operation signal EN input from the outside; and when the operation signal EN input to the first transfer gate is ON, the first phase is greater than or equal to the first phase according to a ratio of current amounts of output signals of the first variable inverter and the second variable inverter. outputting the third output clock signal having a third phase equal to or less than a second phase, and outputting the output of the first variable inverter when the operation signal EN input to the first transfer gate is OFF and a fifth inverter outputting the third output clock signal. Accordingly, the electromagnetic interference characteristic is minimized by outputting a clock signal having various phases between the two input clock signals Clock.

Description

DEVICE OF CONTROLLING PHASE CLOCK FOR LOW EMI CHARACTERISTIC

The present invention relates to an apparatus for controlling a phase of a clock signal to reduce electromagnetic interference, and more particularly, to a synchronous memory using a clock signal or to a wired/wireless communication field where EMI is a problem. It relates to a communication circuit with interference characteristics.

In the case of electronic devices that perform tasks through data arithmetic processing, such as smartphones, tablet PCs, and computers, communication between the central processing unit (CPU) and the memory is performed. Among them, in the process of reading data stored in the memory from the central processing unit, a plurality of memory output drivers output data at the same clock time.

In the process, multiple output drivers flow a large amount of current at once. When a large amount of current is used at once, the voltage of the VDD rail becomes unstable, which causes electromagnetic waves to be generated. As the degree of integration between chips of electronic devices increases, electromagnetic waves generated inside a chip may cause EMI (Electro Magnetic Interference) and may directly affect the operation of other chips.

In the case of the existing output driver, since data is read at the same clock time, a large amount of current is consumed at once, which causes a problem such as EMI. When EMI occurs, it can affect the operation of other chips and also affect communication between chips within the PCB, which can seriously affect the overall operation of electronic devices.

The existing DDR4 (Double Data Rate 4) SDRAM (Synchronous DRAM) receives a differential clock signal from the outside and divides the frequency in half to reduce the timing margin and power consumption of data. Signals with phases of 0°, 90°, 180° and 270° can be used. At this time, all output drivers are synchronized to a clock signal with a phase of 0°, and data switching occurs at the same time when data is read.

1 shows a circuit of a conventional output driver. FIG. 2 is a timing diagram of a data reading process of the conventional output driver of FIG. 1 .

1 and 2 , the clock signal is generated by clock signals of 0°, 90°, 180°, and 270° entering the output terminal. Data is output in synchronization with this clock signal.

As shown in FIG. 2 , when data is switched at the same time, the amount of current used at one time increases, so there is a problem in that EMI (Electro Magnetic Interference) characteristics are deteriorated due to an increase in electromagnetic waves.

US 8664993 B1 KR 2003/0005771 A KR 1584426 B1

Accordingly, it is an object of the present invention to provide an apparatus for controlling the phase of a clock signal with improved electromagnetic interference (EMI) characteristics by reducing the amount of current used at a time by varying the data switching time. will be.

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A clock signal phase control apparatus for reducing electromagnetic interference according to an embodiment for realizing the above object of the present invention includes a first output having a first phase based on a first input clock signal having a first phase a first inverter and a second inverter outputting a clock signal; a third inverter and a fourth inverter outputting a second output clock signal having a second phase based on a second input clock signal having a second phase; a first variable inverter passing the first input clock signal to generate a third output clock signal; a second variable inverter for transferring the second input clock signal to generate the third output clock signal; a first transmission gate connected to an output terminal of the second variable inverter and configured to change a path of an output signal of the second variable inverter according to an operation signal EN input from the outside; and when the operation signal EN input to the first transfer gate is ON, the first phase is greater than or equal to the first phase according to a ratio of current amounts of output signals of the first variable inverter and the second variable inverter. outputting the third output clock signal having a third phase equal to or less than a second phase, and outputting the output of the first variable inverter when the operation signal EN input to the first transfer gate is OFF and a fifth inverter outputting the third output clock signal.

In an embodiment of the present invention, the fifth inverter converts the output of the first variable inverter to the third output clock signal when the operation signal EN input to the first transfer gate is OFF. can be printed out.

In an embodiment of the present invention, in order to delay the output time of the output signal of the first variable inverter to be equal to the output time of the first transfer gate, a second variable inverter connected between the first variable inverter and the fifth inverter It may further include a transmission gate.

In an embodiment of the present invention, a third transfer gate connected between the first inverter and the second inverter to delay the output time of the first output clock signal to be equal to the output time of the third output clock signal ; and a fourth transfer gate connected between the third inverter and the fourth inverter to delay an output time of the second output clock signal equal to an output time of the third output clock signal. have.

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According to the apparatus for controlling the phase of a clock signal to reduce electromagnetic interference, a phase of a clock signal with a fixed phase between two input clock signals is not output by using a variable inverter, but a phase may be varied. Accordingly, by reducing the amount of current consumed at once by varying the data switching time, electromagnetic waves that may be generated inside the chip can be reduced, thereby minimizing the problem caused by EMI (Electro Magnetic Interference).

1 shows a circuit of a conventional output driver.
FIG. 2 is a timing diagram illustrating a data reading process of the conventional output driver of FIG. 1 .
3 is a circuit diagram illustrating an example of an output driver including a phase controller according to the present invention.
4 is a circuit diagram of a phase controller according to the present invention.
FIG. 5 is a diagram illustrating only a circuit diagram between two clock signals in the phase controller of FIG. 4 .
6 is a timing diagram illustrating a data reading process of the output driver of FIG. 3 .
7 is a diagram illustrating an operation process of changing a path of an output signal during an ON operation of the phase controller according to the present invention.
8 is a diagram illustrating an operation process of changing a path of an output signal during an OFF operation of the phase controller according to the present invention.
9 is a graph comparing the amount of current of the conventional output driver of FIG. 1 and the amount of current of the output driver of FIG. 3 according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0010] Reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. In addition, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present invention, if properly described, is limited only by the appended claims, along with all scope equivalents as those claimed. Like reference numerals in the drawings refer to the same or similar functions throughout the various aspects.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

3 is a circuit diagram illustrating an example of an output driver including a phase controller according to the present invention.

The phase control device 50 (hereinafter, referred to as the phase control device) of a clock signal for reducing electromagnetic interference according to the present invention is an electromagnetic interference ( It has a circuit structure that changes the phase of the clock signal to solve the Electro Magnetic Interference (EMI) problem.

Referring to FIG. 3 , an example of an output driver 1 of a memory (DDR4 (Double Data Rate 4) SDRAM (Synchronous DRAM)) to which the phase control device 50 according to the present invention is applied, the amplifier 10 shown ), the frequency divider 30 and the output terminals (Byte 0, Byte 1, Byte 2, Byte 3) are merely exemplary, and each element can be deleted or changed, and other elements can be added.

The amplifier 10 (Amp) receives and amplifies a pair of differential clock signals CLK and CLKB, and the frequency divider 30 (Freq. DIV(/2)) receives the amplified differential clock signal Divide the frequency of (CLK, CLKB).

For example, the frequency divider 30 divides the frequencies of the amplified differential clock signals CLK and CLKB in half and divides them into four clock signals having phases of 0°, 90°, 180°, and 270°. can be printed out.

The conventional output driver as shown in Figure 1 is based on the four clock signals (CLK 0 °, CLK 90 °, CLK 180 °, CLK 270 °) having the phases of 0 °, 90 °, 180 °, 270 °, When data is read in synchronization with a clock signal having a phase of 0° (CLK in FIG. 2), all data switching occurs at the same timing.

On the other hand, when the phase control device 50 proposed in the present invention is applied, clock signals (CLK 0°, CLK 90°, CLK 180°, CLK) having phases of 0°, 90°, 180°, and 270° 270°), the first clock signal CLK0 is generated, and the clock signals CLK Φ°, CLK Φ+90°, The second clock signal CLK1 is generated by CLK Φ+180° and CLK Φ+270°).

Accordingly, by using the phase control device 50 proposed in the present invention, the timing of reading data can be effectively dispersed using a clock signal having a phase difference between clock signals smaller than 1 UI bit. have.

Hereinafter, the phase control device 50 proposed by the present invention will be described in detail.

4 is a circuit diagram of a phase controller according to the present invention. FIG. 5 is a diagram illustrating only a circuit diagram between two clock signals in the phase controller of FIG. 4 .

The phase control device 50 may turn on/off a function by using a transfer gate, rather than output a clock signal having a fixed phase between two input clocks using a variable inverter. The phase can be changed.

Referring to FIG. 4 , a clock signal having 8 phases (CLK Φ°, CLK Φ+90°) is received by receiving a clock signal having four phases (CLK 0°, CLK 90°, CLK 180°, CLK 270°). , CLK Φ+180°, CLK Φ+270°). Here, Φ is a real number greater than or equal to 0 and less than or equal to 90.

To this end, each clock signal (CLK 0°, CLK 90°, CLK 180°, CLK 270°) is a clock signal (CLK Φ°, CLK Φ+90°, CLK Φ+180°, CLK Φ+270°).

Specifically, a first input clock signal CLK 0° having a first phase (0°), a second input clock signal CLK 90° having a second phase (90°), and a third phase (180°) A third input clock signal CLK 180° having a and a fourth input clock signal CLK 270° having a fourth phase 270° are input to the phase control device 50 .

Here, the first phase, the second phase, the third phase, and the fourth phase each have phases of 0°, 90°, 180°, and 270°, for example, but this is changeable and each phase difference is constant It may have a difference (eg, having a phase of 30°, 120°, 210°, 300°).

The phase control device 50 includes the first input clock signal CLK 0°, the second input clock signal CLK 90°, the third input clock signal CLK 180°, and the fourth input clock signal. _{Output clock signals (CLK OUT} 0°, CLK _OUT 90°, CLK _OUT 180°, CLK _OUT 270°) each having the same phase as (CLK 270°) are output.

In addition, the phase control device 50 is an output clock signal having a phase between 0° and 90° based on the first input clock signal CLK 0° and the second input clock signal CLK 90°. An output clock signal that outputs (CLK _OUT Φ°) and has a phase between 90° and 180° based on the second input clock signal CLK 90° and the third input clock signal CLK 180° (CLK _OUT Φ+90°) is output.

Similarly, the phase control device 50 may generate an output clock signal having a phase between 180° and 270° based on the third input clock signal CLK 180° and the fourth input clock signal CLK 270°. (CLK _OUT Φ+180°) and output having a phase between 270° and 0° based on the fourth input clock signal CLK 270° and the first input clock signal CLK 0° A clock signal (CLK _OUT Φ+270°) is output.

To this end, a phase control circuit including a variable inverter and transfer gates is configured between two adjacent input clock signals. A phase control circuit between the first input clock signal CLK 0° and the second input clock signal CLK 90° is representatively described in FIG. 5 .

Referring to FIG. 5 , the phase control device 50 has a first phase (0°) based on the first input clock signal CLK 0° and the second input clock signal CLK 90°. A first output clock signal (CLK _OUT 0°), a second output clock signal (CLK _OUT 90°) having a second phase (90°), and between the first phase (0°) and the second phase (90°) A third output clock signal CLK _OUT Φ° having a phase of is output.

In other words, the phase control device 50 adjusts the phases of the two input clock signals CLK 0° and CLK 90°, and the first to third output clock signals CLK _OUT 0° and CLK _{OUT having different phases from each other.} 90°, CLK _OUT Φ°).

To this end, the phase control device 50 includes five inverters 110, 130, 150, 170, 190, two variable inverters ( 310, 330, Inverter) and four transmission gates 510, 530, 550, and 570 (Transmission Gate).

Specifically, the phase control device 50 includes a first input clock signal CLK 0° having the first phase (0°) and a second input clock signal CLK 90 having the second phase (90°). °) between the first inverter 110, the second inverter 150, the third inverter 130, the fourth inverter 190, the fifth inverter 170, the first variable inverter 310, the second variable It includes an inverter 330 and a first transfer gate 550 .

The first inverter 110 and the third inverter 130 receive the first input clock signal CLK 0° and the second input clock signal CLK 90°, respectively, and the second inverter 150 , the fourth inverter 190 and the fifth inverter 170 respectively output the first to third output clock signals CLK _OUT 0°, CLK _OUT 90°, and CLK _OUT Φ°.

In addition, second to fourth transmission gates serving as dummy transmission gates for synchronizing output times of the output clock signals CLK _OUT 0°, CLK _OUT 90°, and CLK _{OUT Φ° (} 510, 530, 570) may be further included.

The first transfer gate 550 receives the operation signal EN as an input and substantially changes the path of the second input clock signal CLK 90°, while the second to fourth transfer gates 510 , 530 and 570 take the operating voltage VDD and the ground voltage GND as inputs, and only control output timing between inverters or variable inverters.

The first inverter 110 and the second inverter 150 have a first phase (0°) based on a first input clock signal (CLK 0°) having a first phase (0°). Outputs the output clock signal (CLK _OUT 0°).

Between the first inverter 110 and the second inverter 150, _{the output timing of the first output clock signal CLK OUT} 0° is identical to the output timing of the third output clock signal CLK _{OUT Φ°.} A second transfer gate 510 may be formed.

The third inverter 130 and the fourth inverter 190 have a second phase (90°) based on a second input clock signal (CLK 90°) having a second phase (90°). Outputs the output clock signal (CLK _OUT 90°).

Between the third inverter 130 and the fourth inverter 190, _{the output timing of the second output clock signal CLK OUT} 90° is identical to the output timing of the third output clock signal CLK _{OUT Φ°.} A fourth transfer gate 570 may be formed.

The first input clock signal CLK 0° and the second input clock signal CLK 90° are respectively input to the first inverter 110 and the third inverter 130, while the first variable It is also input to the inverter 310 and the second variable inverter 330 .

The first variable inverter 310 outputs the first input clock signal CLK 0° to the connected third transfer gate 530 , and the second variable inverter 330 outputs the second input clock signal CLK 90°) to the connected first transfer gate 550 .

The first transfer gate 550 is connected between the second variable inverter 330 and the fifth inverter 170, and according to ON and OFF of the operation signal EN, the The path of the output signal of the second variable inverter 330 is changed.

Accordingly, the fifth inverter 170 is higher than the first phase (0°) based on the output signals of the first variable inverter 310 and the second variable inverter 330 and the second phase ( 90°) or less, a third output clock signal having a third phase (Φ°) or a third output clock signal having the same phase (0°) as _{the first output clock signal (CLK OUT 0°) is output.}

That is, when the operation signal EN input to the first transfer gate 550 is ON, based on the output signals of the first variable inverter 310 and the second variable inverter 330 , _{A third output clock signal CLK OUT} Φ° having a third phase Φ° that is greater than or equal to the first phase (0°) and less than or equal to the second phase (90°) is output through the fifth inverter 170 . do.

On the other hand, when the operation signal EN input to the first transfer gate 550 is OFF, the output of the first variable inverter 310 is converted to the third output clock signal by the fifth inverter ( 170) to output it. At this time, the output of the third output clock signal is delayed through the third transfer gate 530 so that the first output clock signal CLK _OUT 0° and the second output clock signal CLK _OUT 90° and may be output at the same timing.

_{Here, the first output clock signal CLK OUT} 0° output from the second inverter 150 is a signal of the same phase (0°) as the first input clock signal CLK 0°, and the fourth inverter The second output clock signal CLK _OUT 90° output at step 190 has the same phase (90°) as the second input clock signal CLK 90°.

When the operation signal EN is OFF, the transmission of the second input clock signal CLK 90° to the third output clock signal is blocked by the first transfer gate 550 , The first input clock signal CLK 0° is equally transmitted as the first output clock signal and the third output clock signal. Accordingly, the first output clock signal and the third output clock signal have the same phase. At this time, the output current amount and the transfer delay value of the first variable inverter 310 are initialized to have the same values as those of the first inverter 110 .

When the operation signal EN is ON, the first input clock signal CLK 0° is applied to the first variable inverter 310 , the third transfer gate 530 , and the fifth inverter 170 . ) through the third output clock signal. The second input clock signal CLK 90° is transmitted as the third output clock signal through the second variable inverter 330 , the first transfer gate 550 , and the fifth inverter 170 .

In this case, according to the ratio of the output current of the first variable inverter 310 and the second variable inverter 330 , the fifth inverter 170 is larger than the phase of the first input clock signal CLK 0° and the The third output clock signal having a phase smaller than that of the second input clock signal CLK 90° is output.

The second transfer gate 510 delays the output timing of the second inverter 150, and the second transfer gate 510 delays the output timing of the fifth inverter 170 when the operation signal EN is OFF The third transmission gate 530 and the fourth transmission gate 570 for delaying the output timing of the fourth inverter 190 are dummy transmission gates, and each output of the phase control device 50 is It was added to reduce the phase error by making the data path similar and making the delay as much as possible.

The phase control device 50 according to the present invention generates eight phases using four phase clock signals. Through this, for example, data of 0 byte can be switched in synchronization with a clock signal having a phase of 0°, and data of 1 byte can be operated in synchronization with a clock signal having a phase of 45°. Here, the time difference between the clock signals having phases of 0° and 45° becomes 0.5 UI, so that simultaneous switching between the output terminals of the output driver 1 does not occur.

6 is a timing diagram illustrating a data reading process of the output driver of FIG. 3 .

CLK0 is made by clock signals of 0°, 90°, 180°, 270° like the conventional output driver of FIG. 2, and CLK1 is Φ+0°, Φ+90°, Φ+180°, Φ+270° generated by the clock signal of

Using the phase control device 50 according to the present invention, the timing of reading data is effectively distributed using a clock signal having a phase difference between clock signals smaller than 1 UI bit.

When the applied device (eg, memory) is in the high-speed high-performance mode, the slew-rate control technique, which is one of the existing EMI reduction methods, cannot be used because 1 UI is short. However, when the phase control device 50 proposed in the present invention is used, the maximum value of the used current is reduced and the EMI characteristic is improved.

On the other hand, when the applied device (eg, memory) is in the low-speed low-power mode, the phase control device 50 proposed in the present invention does not use the current distribution method and only uses the slew-rate control method so that the transmission gate ( TG) can be added to turn on/off the function.

Hereinafter, the operation by ON/OFF of the operation signal EN in the phase control device 50 proposed by the present invention will be described once again.

7 is a diagram illustrating an operation process of changing a path of an output signal during an ON operation of the phase controller according to the present invention. 8 is a diagram illustrating an operation process of changing a path of an output signal during an OFF operation of the phase controller according to the present invention.

The first transmission gate 550 receives the operation signal EN as an ON/OFF signal from an external controller and changes the path of the output signal of the phase control device 50 . The operation process of the phase control device 50 in this case can be confirmed through FIGS. 7 and 8 .

Referring to FIG. 7 , for example, when a clock signal CLK _{IN_0} , CLK _{IN_90} having a phase of 0° and 90° is interpolated by receiving as an input, the operation signal EN is ON. In this case, the output signal CLK _{OUT_PI_1} is a clock signal having a phase of a value between 0° and 90°.

Referring to FIG. 8 , when the operation signal EN is OFF, a path of a clock signal having a phase of 90° of an interpolator is blocked using a switch. Accordingly, the output signal (CLK _{OUT_PI_1)} is the output signal becomes like all the rest of the output signal (CLK _{OUT_0)} having a phase of 0 ° outgoing path having a phase of 0 ° _{(OUT_0} CLK) is output.

Accordingly, when the function of the phase control device 50 according to the present invention is OFF, the timing diagram of the entire circuit becomes the same as the timing diagram of FIG. 2 .

9 is a graph comparing the amount of current of the conventional output driver of FIG. 1 and the amount of current of the output driver of FIG. 3 according to the present invention.

Referring to FIG. 9 , although the average current consumption of the output driver is similar, the peak current, which appears high when a large amount of current is used at once, is 23% in the output driver to which the phase control device 50 according to the present invention is applied. decreased to some extent.

Accordingly, the present invention reduces the amount of current consumed at a time by varying the data switching time, thereby reducing electromagnetic waves that may be generated inside the chip, thereby minimizing the problem due to electromagnetic interference.

Although the above has been described with reference to the embodiments, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below you will understand

The present invention is applied to a wired/wireless communication field in which a synchronous memory using a clock signal or EMI is a problem, and in particular, can be usefully applied to a communication circuit with low electromagnetic interference characteristics for IoT devices.

1: output driver
10: amplifier
30: frequency divider
50: phase control device
110, 130, 150, 170, 190: Inverter
310, 330: variable inverter
510, 530, 550, 570: transfer gate

Claims (4)

a first inverter and a second inverter for outputting a first output clock signal having a first phase based on a first input clock signal having a first phase;
a third inverter and a fourth inverter outputting a second output clock signal having a second phase based on a second input clock signal having a second phase;
a first variable inverter passing the first input clock signal to generate a third output clock signal;
a second variable inverter for transferring the second input clock signal to generate the third output clock signal;
a first transfer gate connected to an output terminal of the second variable inverter and configured to change a path of an output signal of the second variable inverter according to an operation signal EN input from the outside; and
When the operation signal EN input to the first transfer gate is ON, the first phase is greater than or equal to the first phase according to a ratio of current amounts of output signals of the first variable inverter and the second variable inverter The third output clock signal having a third phase equal to or less than two phases is output, and when the operation signal EN input to the first transfer gate is OFF, the output of the first variable inverter is output to the second A fifth inverter outputting the 3 output clock signal; including, a clock signal phase control device for reducing electromagnetic interference.
According to claim 1,
A second transfer gate connected between the first variable inverter and the fifth inverter to delay the output time of the output signal of the first variable inverter to be equal to the output time of the first transfer gate; , a clock signal phase control device to reduce electromagnetic interference.
According to claim 1,
a third transfer gate connected between the first inverter and the second inverter to delay an output time of the first output clock signal equal to an output time of the third output clock signal; and
A fourth transmission gate connected between the third inverter and the fourth inverter to delay an output time of the second output clock signal equal to an output time of the third output clock signal; Phase control device for clock signal to reduce interference.
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