KR20030005771A - Delay locked loop circuit capable of controlling delay time according to the period of external clock and memory device including the same - Google Patents

Abstract

PURPOSE: A DLL circuit capable of adjusting delay time according to period of external clock signal is provided to be capable of reducing the number of delay stages for compensating a delay time. CONSTITUTION: A period classifying circuit(210) senses a period of the first clock signal(CLK1) and generates period classification signals(Q1,Q2) for classifying the period of the first clock signal(CLK1). A control voltage generating circuit(230) generates a control voltage(CV) for controlling a delay time of delay stages in a delay line(250), based on logic states of the first and second period classification signals(Q1,Q2). A phase detector(270) compares the first clock signal(CLK1) with the second clock signal(CLK2) to generate a detection signal(PD) indicating a phase error between the first and second clock signals(CLK1,CLK2). A control circuit(290) responds to the detection signal(PD) and generates control signals(CNT) for controlling the delay stages in the delay line(250), respectively. The delay line(250) responds to the control voltage(CV) and the control signals(CNT) and delays the first clock signal(CLK1) to generate the second clock signal(CLK2) synchronized with the first clock signal(CLK).

Description

Delay locked loop circuit capable of controlling delay time according to the period of external clock and memory device including the same}

The present invention relates to a semiconductor memory device, and more particularly, to a DLL circuit capable of adjusting a delay time according to an external clock cycle and a memory device including the same.

The conventional delay locked loop (DLL) circuit includes a plurality of delay cells, a control circuit for controlling the operation of the delay stages, and a phase detector. The phase detector compares the phase between the external clock and the internal clock. Thus, the number of delay stages is increased / decreased by the compared phase difference, so that the phase of the external clock and the phase of the internal clock are synchronized. The delay stage is designed to have a constant delay (unit delay), and a large number of delay stages are selected when a large delay is required, and a small delay stage is selected when a small delay is needed.

The cycle of the external clock and the number of delay stages are proportional. That is, when the period of the external clock is large, a lot of delay is required, so a delay stage is used a lot. If the period of the external clock is small, the delay stage is used less. For example, if the unit delay of the delay stage is 500 (ps) and the period of the external clock can be increased up to 10 (ns), the total number of delay stages constituting the delay line is 10n / 500p = 20 (Dog)

The disadvantage of the prior art is that as the period of the external clock increases, the number of necessary delay stages increases, which takes a long time to compensate for the delay. Since the current flowing in the DLL circuit is proportional to the number of delay stages used, when the number of delay stages increases, the current flowing in the entire DLL circuit increases. In addition, since the limited size of the semiconductor chip does not allow the number of delay stages to be infinitely increased, the period of the external clock that the DLL circuit can compensate may be limited. Therefore, a typical DDL (Double Data Rate) SDRAM (SDRAM; SYNCRONOUS DRAM) in which a conventional DLL circuit is used is specified so as not to be used when the external clock period is 15 (ns) or more.

An object of the present invention is to provide a DLL circuit that can reduce the number of delay stages required for delay compensation.

Another object of the present invention is to provide a memory device including the DLL circuit.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the DLL circuit shown in FIG. 1.

FIG. 3 is a circuit diagram illustrating the periodic classification circuit of FIG. 2 in detail.

4 is a timing diagram illustrating an operation of the periodic classification circuit of FIG. 3.

5 is a table showing the state of the periodic classification signal of FIG. 3 according to the magnitude of the period of the first clock.

FIG. 6 is a circuit diagram illustrating an embodiment of a delay stage included in the delay line of FIG. 2.

FIG. 7 is a circuit diagram illustrating another embodiment of a delay stage included in the delay line of FIG. 2.

In order to achieve the above object, the DLL circuit of the present invention relates to a DLL circuit for generating a second clock in synchronization with the first clock. The DLL circuit of the present invention generates a period classification circuit for generating period classification signals for classifying the period of the first clock in response to the period of the first clock, and generates a control voltage in response to the period classification signals. And a delay line including a plurality of delay stages to generate the second clock by delaying the first clock in response to a control voltage generation circuit and the control voltage. When the period of the first clock is small, the delay time of each of the delay stages is small, and when the period of the first clock is large, the delay time of each of the delay stages is increased.

According to a preferred embodiment, the periodic classification circuit includes a first delay circuit for delaying the first clock to generate a first delay clock, and the periodic classification signals in response to the first clock and the first delay clock. A first flip flop for generating a first periodic classification signal, a second delay circuit for delaying the first delay clock to generate a second delay clock, and in response to the first clock and the second delay clock, And a second flip-flop for generating a second period classification signal among the period classification signals.

In addition, each of the delay stages is a differential amplifier type delay stage, and the resistance of the power stage included in the differential amplifier type delay stage may be adjusted by the control voltage, and the differential amplifier type is controlled by the control voltage. The current source included in the delay stage of may be adjusted.

The DLL circuit of the present invention can speed up the delay compensation and reduce the current flowing through the DLL circuit. In addition, the period of the external clock that the DLL circuit can compensate can be increased.

In order to achieve the above another object, a memory device of the present invention relates to a memory device for outputting data in synchronization with a first clock. The memory device of the present invention is synchronized with a memory cell array for storing data, an output buffer for outputting data read from the memory cell array, and a first clock for controlling the output timing of the output buffer from the first clock. And a DLL circuit for generating the second clock. The DLL circuit includes a plurality of delay stages. When the period of the first clock is small by classifying the period of the first clock, the delay time of each of the delay stages is reduced, and the period of the first clock is increased. If large, the delay time of each of the delay stages may be increased.

According to a preferred embodiment, the DLL circuit comprises a periodic classification circuit for generating periodic classification signals for classifying the period of the first clock in response to the period of the first clock, and in response to the periodic classification signals. And a control line generating circuit for generating a voltage, and a delay line including the plurality of delay stages to generate the second clock by delaying the first clock in response to the control voltage.

The periodic classification circuit may include a first delay circuit configured to delay the first clock to generate a first delay clock, and a first periodic classification signal of the periodic classification signals in response to the first clock and the first delay clock. A first flip-flop for generating a second delay circuit; a second delay circuit for delaying the first delay clock to generate a second delay clock; and in response to the first clock and the second delay clock, among the periodic classification signals. And a second flip flop for generating a second periodic classification signal.

Since the memory device of the present invention includes the DLL circuit, the current flowing through the memory device of the present invention can be reduced, and the period of the external clock input to the memory device of the present invention can be increased.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1, a memory device according to an embodiment of the present invention includes a memory cell array 110, a sense amplifier 115, a column decoder 120, and a row decoder 105. The external clock ECLK becomes the first clock CLK1 through the input buffer 125. The first clock CLK1 is applied to the DLL circuit 200.

The DLL circuit 200 controls the second clock CLK2 for controlling the output timing of the read data of the output buffer 130 and includes a plurality of delay stages. The DLL circuit 200 classifies the period of the first clock CLK1, and when the period of the first clock CLK1 is small, decreases the delay time of the delay stage, and when the period of the first clock CLK1 is large. The delay time of the delay stage is increased. Thus, the DLL circuit 200 delays the classified first clock CLK1 to generate a second clock CLK2 that makes the phase of DQ coincide with the phase of the external clock ELCK.

FIG. 2 is a block diagram illustrating an embodiment of the DLL circuit shown in FIG. 1. Referring to FIG. 2, the DLL circuit 200 according to an embodiment of the present invention includes a periodic classification circuit 210, a control voltage generation circuit 230, a delay line 250, a phase detector 270, and a control circuit ( 290.

The period classification circuit 210 detects the period of the first clock CLK1 and generates period classification signals Q1 and Q2 that classify the period of the first clock CLK1 according to the magnitude of the period. The first clock CLK1 is a clock input from the outside of the memory device.

The control voltage generation circuit 230 controls the delay time of the plurality of delay stages included in the delay line 250 according to the states of the first period classification signal and the second period classification signal Q1 and Q2. Will occur).

The phase detector 270 compares the first clock CLK1 and the second clock CLK2 and generates a detection signal PD for detecting a phase difference between the first clock CLK1 and the second clock CLK2.

In response to the detection signal PD, the control circuit 290 generates control signals CNT for controlling the operations of the plurality of delay stages included in the delay line 250.

The delay line 250 delays the first clock CLK1 in response to the control voltage and the control signals CV and CNT to generate a second clock CLK2 synchronized with the first clock CLK.

FIG. 3 is a circuit diagram illustrating the periodic classification circuit of FIG. 2 in detail. Referring to FIG. 3, the periodic classification circuit 210 includes a first delay circuit 211, a D flip flop 213, a second delay circuit 215, and a D flip flop 217. The period classification circuit 210 may further include flip-flops other than the D flip-flops 213 and 217 to more accurately classify the period of the first clock CLK.

The first delay circuit 211 delays the first clock CLK1 by a predetermined delay time. The second delay circuit 215 delays the first delay clock DCK1 by a predetermined delay time. Preferably, the delay time of the first delay circuit 211 and the second delay circuit 215 may be the same value d.

4 is a timing diagram illustrating an operation of the periodic classification circuit of FIG. 3. 4 is a timing diagram corresponding to the case where the period tCK of the first clock CLK1 is larger than 4d (tCK> 4d). 3 and 4, the operation of the periodic classification circuit 210 will be described. The first clock CLK1 is input to the D terminal of the D flip-flop 213 at a period tCK. The first clock CLK1 is delayed by the first delay circuit 211 by the delay time d to become the first delay clock DCK1. The first delay clock DCK1 is input to the clock terminal CK of the D flip-flop 213. Then, when the first delay clock DCK1 rises at the rising edge, the first clock CLK1 is latched so that the first period classification signal Q1 is brought into a "high" state.

In addition, the first clock CLK1 is applied to the D terminal of the D flip-flop 217. The first delay clock DCK1 is delayed by the delay time d by the second delay circuit 215 to become the second delay clock DCK2. The second delay clock DCK2 is input to the clock terminal CK of the D flip-flop 217. Then, when the second delay clock DCK2 rises at the rising edge, the first clock CLK1 is latched so that the second period classification signal Q2 is brought into a "high" state.

5 is a table showing the state of the period classification signal according to the magnitude of the period of the first clock. Referring to FIG. 5, the state of the periodic classification signals Q1 and Q2 varies according to the magnitude relationship between the period tCK of the first clock CLK1 and the delay time d. That is, the first clock CLK1 may be classified according to the value of the first clock period tCK. If the delay time d is shortened, the first clock CLK1 may be classified more finely.

The delay stage included in the delay line is designed so that the magnitude of the delay does not change according to process, temperature, and voltage changes. The delay stage is generally configured in the form of a differential amplifier, and the delay stage in the form of a differential amplifier adjusts the resistance of the power stage or the current of the current source to adjust the delay time.

6 is a circuit diagram illustrating an embodiment of a delay stage included in the delay line of FIG. 2. Referring to FIG. 6, the PMOS transistor MP and the resistor R are specifically illustrated in the delay stage 251 in the form of a differential amplifier, and the portion 253 of the delay stage 251 other than this is not specifically illustrated. Do not.

An operation in which the resistance of the power supply stage is adjusted to adjust the delay time is described. The delay time is large when the resistance is large and becomes small when the resistance is small. The control voltage CV generated by the control voltage generation circuit 230 of FIG. 2 becomes the gate voltage Vg of the PMOS transistor MP. The ON resistance Ron of the PMOS transistor MP varies depending on the state of the gate voltage Vg.

When the gate voltage Vgs for the source drops below the threshold voltage Vth, a channel is generated in the PMOS transistor MP. Then, the on resistance Ron and the resistor R are connected in parallel, and the resistance value becomes Ron // R. On the contrary, if the gate voltage Vgs of the source rises above the threshold voltage Vth, no channel is formed. Then, the on resistance Ron becomes almost infinity and the resistance value becomes almost R. Therefore, the on resistance Ron changes in accordance with the gate voltage Vg, whereby the delay time may change.

FIG. 7 is a circuit diagram illustrating another embodiment of a delay stage included in the delay line of FIG. 2. Referring to FIG. 7, the NMOS transistor MN is specifically illustrated in the delay stage 261 in the form of a differential amplifier, and a portion 263 of the delay stage 261 other than this is not specifically illustrated.

An operation in which the current source included in the delay stage 261 in the form of a differential amplifier is adjusted to adjust the magnitude of the delay is described. The control voltage CV generated by the control voltage generation circuit 230 of FIG. 2 becomes the gate voltage Vg of the NMOS transistor MN. When the gate voltage Vg rises, the delay time decreases. Therefore, the delay time may be adjusted by adjusting the gate voltage Vg.

Therefore, the DLL circuit according to the present invention can classify the periods of the external clock so that the delay time of the delay stage is small when the cycle of the external clock is small, and the delay time of the delay stage can be increased when the cycle is large. Thus, the number of delay stages required for delay compensation can be reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. .

The DLL circuit of the present invention can speed up the delay compensation and reduce the current flowing through the DLL circuit. In addition, the period of the external clock that the DLL circuit can compensate can be increased.

Since the memory device of the present invention includes the DLL circuit, the current flowing through the memory device of the present invention can be reduced, and the period of the external clock input to the memory device of the present invention can be increased.

Claims (10)

In the DLL circuit which generates a second clock in synchronization with the first clock, A period classification circuit for generating period classification signals for classifying the period of the first clock in response to the period of the first clock; A control voltage generation circuit for generating a control voltage in response to the periodic classification signals; And A delay line including a plurality of delay stages, wherein the second clock is generated by delaying the first clock in response to the control voltage; The delay time of each of the delay stages decreases when the period of the first clock is small, and the delay time of each of the delay stages increases when the period of the first clock is large. The method of claim 1, wherein the periodic classification circuit A first delay circuit for delaying the first clock to generate a first delay clock; A first flip-flop that generates a first period classification signal among the period classification signals in response to the first clock and the first delay clock; A second delay circuit for delaying the first delay clock to generate a second delay clock; And And a second flip-flop that generates a second periodic classification signal among the periodic classification signals in response to the first clock and the second delay clock. The method of claim 2, wherein the first flip-flop and the second flip-flop D flip-flop DLL circuit characterized in that. The method of claim 2 or 3, wherein each of the delay stages And a differential amplifier type delay stage, wherein the resistance of the power supply stage included in the differential amplifier type delay stage is controlled by the control voltage. The method of claim 2 or 3, wherein each of the delay stages And a differential amplifier type delay stage, wherein a current source included in the differential amplifier type delay stage is controlled by the control voltage. A memory device for outputting data in synchronization with a first clock, A memory cell array for storing data; An output buffer configured to output data read from the memory cell array; A DLL circuit for generating a second clock synchronized with the first clock for controlling the output timing of the output buffer from the first clock, The DLL circuit includes a plurality of delay stages. When the period of the first clock is small by classifying the period of the first clock, the delay time of each of the delay stages is reduced, and the period of the first clock is increased. If large, delay time of each of the delay stages is increased. The method of claim 6, wherein the DLL circuit is A period classification circuit for generating period classification signals for classifying the period of the first clock in response to the period of the first clock; A control voltage generation circuit for generating a control voltage in response to the periodic classification signals; And And a delay line configured to delay the first clock to generate the second clock in response to the control voltage and to include the plurality of delay stages. The method of claim 7, wherein the periodic classification circuit is A first delay circuit for delaying the first clock to generate a first delay clock; A first flip-flop that generates a first period classification signal among the period classification signals in response to the first clock and the first delay clock; A second delay circuit for delaying the first delay clock to generate a second delay clock; And And a second flip-flop that generates a second periodic classification signal among the periodic classification signals in response to the first clock and the second delay clock. The method of claim 7 or 8, wherein each of the delay stages And a differential amplifier type delay stage, wherein a resistance of a power supply stage included in the differential amplifier type delay stage is adjusted by the control voltage. The method of claim 7 or 8, wherein each of the delay stages And a differential amplifier type delay stage, wherein a current source included in the differential amplifier type delay stage is controlled by the control voltage.