JP2016012204A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To offset a deviation of a duty ratio due to an internal factor.SOLUTION: A semiconductor device includes: a clock tree 114 that receives an input of an internal clock signal LCLK1 and outputs an internal clock signal LCLK; an offset detection circuit 180 that detects a difference between a duty ratio of the internal clock signal LCLK and a predetermined duty ratio (50%) so as to generate an offset signal OF; and a duty offset circuit 161 that offsets the duty ratio of the internal clock signal LCLK1 on the basis of the offset signal OF so as to generate an internal clock signal LCLK2. The offset detection circuit 180 and duty offset circuit 161 are integrated on an identical semiconductor chip. According to the present invention, a deviation of the duty radio due to an internal factor can be automatically offset inside the semiconductor device.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a duty correction circuit that adjusts the duty ratio of an internal clock signal.

  A DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, is mainly a type called a DDR (Double Data Rate) type. Since the DDR type DRAM inputs and outputs data in synchronization with both the rising edge and falling edge of the internal clock signal, it is necessary to maintain the duty ratio of the internal clock signal accurately at 50%. In many cases, a duty correction circuit is used (see Patent Document 1).

  Here, external factors and internal factors exist as factors that cause the duty ratio of the internal clock signal to deviate from 50%. An external factor is attributed to an external clock signal, and occurs when the duty ratio of the external clock signal deviates from 50% in the first place. On the other hand, the internal factor is a factor caused by the transmission path in the semiconductor device, and is a phenomenon in which the deviation of the duty ratio increases while the internal clock signal passes through the transmission path.

JP 2008-210436 A

  In order to reduce the deviation of the duty ratio due to an internal factor, it is effective to monitor the duty ratio of the internal clock signal in a portion closer to the output buffer. However, in this case, since the loop length of the feedback loop for duty correction becomes long, the inherent delay time increases. In addition, since a signal path for supplying the control signal obtained by the monitor to the duty correction circuit becomes long, there is a problem that characteristic variation is likely to occur particularly when the control signal is an analog value.

  As a method for solving such a problem, the duty ratio of the internal clock signal is monitored at the input portion of the clock tree, and the duty ratio shift caused by the propagation of the internal clock signal through the clock tree is detected by the duty offset circuit. A method of offsetting can be considered.

  However, conventionally, since it is necessary to detect the deviation of the duty ratio by an external tester, it has been difficult to obtain high detection accuracy. In addition, it takes time to detect the tester and program the duty offset circuit, which increases the manufacturing cost.

  A semiconductor device according to an aspect of the present invention generates a first duty detection signal by detecting a clock tree in which a clock signal propagates and a duty ratio of the clock signal input to the clock tree. A detection circuit; a second duty detection circuit that generates a second duty detection signal by detecting a duty ratio of the clock signal output from the clock tree; and the first and second duty detection signals. And a duty correction circuit for adjusting a duty ratio of the clock signal based on the duty ratio.

  A semiconductor device according to another aspect of the present invention provides a clock tree that receives a first clock signal and outputs a second clock signal, and a difference between a duty ratio of the second clock signal and a predetermined duty ratio. An offset detection circuit that generates an offset signal by detecting, and a first duty offset circuit that generates a third clock signal by offsetting a duty ratio of the first clock signal based on the offset signal; The offset detection circuit and the first duty offset circuit are integrated on the same semiconductor chip.

  According to the present invention, the deviation of the duty ratio due to internal factors can be automatically canceled inside the semiconductor device. For this reason, it is possible to adjust the duty ratio with higher accuracy than in the case of using an external tester, and to reduce the manufacturing cost.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. 2 is a block diagram showing a configuration of a DLL circuit 100. FIG. 3 is a circuit diagram of a duty offset circuit 161. FIG. 3 is a flowchart for explaining a duty correction operation by a DLL circuit 100. It is a wave form diagram which shows an example of the duty ratio of internal clock signal PCLK0, LCLK1, LCLK, and has shown the case where the offset amount by the duty offset circuit 161 is zero. It is a wave form diagram which shows an example of the duty ratio of internal clock signals LCLK and LCLK3. FIG. 7 is a waveform diagram for explaining the relationship between internal clock signal LCLK1 and internal clock signal LCLK2. It is a wave form diagram which shows an example of the duty ratio of internal clock signal PCLK0, LCLK1, and LCLK, and has shown the case where the duty offset circuit 161 is performing offset operation | movement based on the offset signal OF.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM and includes a memory cell array 11 as shown in FIG. The memory cell array 11 is provided with a plurality of word lines WL and a plurality of bit lines BL intersecting with each other, and memory cells MC are arranged at the intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. Each bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 14, and the bit line BL selected by the column decoder 13 is connected to the amplifier circuit 15 through the sense amplifier SA.

  The operations of the row decoder 12, column decoder 13, sense circuit 14, and amplifier circuit 15 are controlled by the access control circuit 20. The access control circuit 20 is supplied with an address signal ADD, a command signal CMD, external clock signals CK, CKB, and the like via external terminals 21-24. The external clock signals CK and CKB are complementary signals. The access control circuit 20 controls the row decoder 12, column decoder 13, sense circuit 14, amplifier circuit 15 and data input / output circuit 30 based on these signals.

  Specifically, when the command signal CMD indicates an active command, the address signal ADD is supplied to the row decoder 12. In response to this, the row decoder 12 selects the word line WL indicated by the address signal ADD, whereby the corresponding memory cell MC is connected to the bit line BL. Thereafter, the access control circuit 20 activates the sense circuit 14 at a predetermined timing.

  On the other hand, when the command signal CMD indicates a read command or a write command, the address signal ADD is supplied to the column decoder 13. In response to this, the column decoder 13 connects the bit line BL indicated by the address signal ADD to the amplifier circuit 15. Thereby, during the read operation, the read data DQ read from the memory cell array 11 via the sense amplifier SA is output to the outside from the data terminal 31 via the amplifier circuit 15 and the data input / output circuit 30. In the write operation, write data DQ supplied from the outside via the data terminal 31 and the data input / output circuit 30 is written into the memory cell MC via the amplifier circuit 15 and the sense amplifier SA.

  As shown in FIG. 1, the access control circuit 20 includes a DLL circuit 100. The DLL circuit 100 is a circuit that receives the external clock signals CK and CKB and generates an internal clock signal LCLK whose phase is controlled based on the external clock signals CK and CKB. The DLL circuit 100 includes a delay line (DL) 110 that delays the internal clock signal LCLK, and a duty correction circuit (DCC) 150 that adjusts the duty ratio of the internal clock signal LCLK to 50%. Details of the DLL circuit 100 will be described later. The internal clock signal LCLK is supplied to an output circuit 30 a included in the data input / output circuit 30. Thereby, the read data DQ and the data strobe signal DQS are output from the data terminal 31 and the data strobe terminal 32 in synchronization with the internal clock signal LCLK, respectively.

  Each of these circuit blocks uses a predetermined internal voltage as an operating power supply. These internal power supplies are generated by the power supply circuit 40 shown in FIG. The power supply circuit 40 receives the external potential VDD and the ground potential VSS supplied through the power supply terminals 41 and 42, and generates the internal potentials VPP, VPERI, VARY, and the like based on these. The internal potential VPP is generated by boosting the external potential VDD, and the internal potentials VPERI and VARY are generated by stepping down the external potential VDD.

  The internal potential VPP is a potential mainly used in the row decoder 12. The row decoder 12 drives the word line WL selected based on the address signal ADD to the VPP level, thereby turning on the cell transistor included in the memory cell MC. The internal potential VARY is a voltage mainly used in the sense circuit 14. When the sense circuit 14 is activated, the read data read out is amplified by driving one of the bit line pairs to the VARY level and the other to the VSS level. The internal potential VPERI is used as an operating voltage for most peripheral circuits such as the access control circuit 20. By using the internal potential VPERI having a lower potential than the external potential VDD as the operating voltage of these peripheral circuits, the power consumption of the semiconductor device 10 is reduced.

  FIG. 2 is a block diagram showing a configuration of the DLL circuit 100.

  The DLL circuit 100 shown in FIG. 2 includes a delay line 110 that generates the internal clock signal LCLK1 by delaying the internal clock signal PCLK1. The internal clock signal PCLK1 is a signal obtained by passing the internal clock signal PCLK0 output from the clock receiver 25 that receives the external clock signals CK and CKB through the duty correction circuit 150. The delay line 110 has a configuration in which a coarse delay line (CDL) 111 having a coarse delay adjustment pitch and a fine delay line (FDL) 112 having a fine delay adjustment pitch are connected in series. The internal clock signal LCLK1 output from the delay line 110 is supplied to the output circuit 30a via the buffer 113 and the clock tree 114, and as described above, as a timing signal that defines the output timing of the read data DQ and the data strobe signal DQS. Used.

  The internal clock signal LCLK1 is also supplied to the replica circuit 120. The replica circuit 120 is a circuit having substantially the same delay time as the circuit group including the buffer 113, the clock tree 114, and the output circuit 30a. The replica circuit 120 receives the internal clock signal LCLK1 and outputs a replica clock signal RCLK. Here, since the output circuit 30a outputs the read data DQ and the data strobe signal DQS in synchronization with the internal clock signal LCLK, the replica clock signal RCLK output from the replica circuit 120 is the read data DQ or data It is precisely synchronized with the strobe signal DQS. In the DRAM, the read data DQ and the data strobe signal DQS need to be accurately synchronized with the external clock signals CK and CKB, and if there is a shift in the phase between them, this is detected and corrected. There is a need to. Such detection is performed by the phase determination circuit 130, and the determination result is output as the phase determination signal PD.

  The phase determination signal PD is supplied to the delay line control circuit 140. The delay line control circuit 140 is a circuit that controls the delay amount of the delay line 110 based on the phase determination signal PD. Specifically, when the phase determination signal PD indicates that the phase of the replica clock signal RCLK is delayed from the internal clock signal PCLK0, the delay line control circuit 140 decreases the delay amount of the delay line 110. Conversely, when the phase determination signal PD indicates that the phase of the replica clock signal RCLK is ahead of the internal clock signal PCLK0, the delay line control circuit 140 increases the delay amount of the delay line 110. By such an operation, the delay amount of the delay line 110 is adjusted so that the phase of the replica clock signal RCLK matches the internal clock signal PCLK0. When the phase of the replica clock signal RCLK matches the internal clock signal PCLK0, the read data DQ and the data strobe signal DQS are accurately synchronized with the external clock signals CK and CKB.

  As shown in FIG. 2, the DLL circuit 100 includes a duty correction circuit 150 that adjusts the duty ratio. Although not particularly limited, in this embodiment, a duty correction circuit 150 is inserted in the preceding stage of the delay line 110, and the internal ratio is adjusted by adjusting the duty ratio of the internal clock signal PCLK0 output from the clock receiver 25. A clock signal PCLK1 is generated. In the present invention, the insertion position of the duty correction circuit 150 is not limited to this, and may be inserted at an arbitrary place, for example, after the delay line 110 as long as it is inserted in the propagation path of the internal clock signal.

  In the present embodiment, the duty ratio of the internal clock signal LCLK is detected at two locations. The first location is a point before being input to the clock tree 114, and the second location is a point after being output from the clock tree 114. In FIG. 2, the internal clock signal input to the clock tree 114 is distinguished as “LCLK1”, and the internal clock signal output from the clock tree 114 is distinguished as “LCLK”.

  First, the internal clock signal LCLK1 input to the clock tree 114 is input to the first duty offset circuit 161 and converted to the internal clock signal LCLK2. The duty offset circuit 161 is a circuit that generates the internal clock signal LCLK2 by offsetting the duty ratio of the internal clock signal LCLK1 based on the offset signal OF, and is used to cancel the deviation of the duty ratio due to internal factors. The internal clock signal LCLK2 is supplied to the first duty detection circuit (DCD) 162.

  The duty detection circuit 162 detects the duty ratio of the internal clock signal LCLK2, and generates the duty detection signal D1 based on this. The duty detection signal D1 is supplied to the DCC control circuit 170. The DCC control circuit 170 receives the duty detection signal D1, generates a duty control signal D0 based on the duty detection signal D1, and supplies it to the duty correction circuit 150. The duty correction circuit 150 changes the duty ratio of the internal clock signal PCLK0 based on the duty detection signal D2, and outputs this as the internal clock signal PCLK1.

  On the other hand, the internal clock signal LCLK output from the clock tree 114 is supplied to the offset detection circuit 180. The offset detection circuit 180 includes a second duty offset circuit 181 and a second duty detection circuit (DCD) 182, and the internal clock signal LCLK is supplied to the duty detection circuit 182 via the duty offset circuit 181. A duty detection signal D2 generated by the duty detection circuit 182 is fed back to the duty offset circuit 181 so that the duty ratio of the internal clock signal LCLK3 output from the duty offset circuit 181 is adjusted to about 50%. The

  FIG. 3 is a circuit diagram of the duty offset circuit 161.

  As shown in FIG. 3, the duty offset circuit 161 includes four clocked inverters CV1, CV2, CV4, and CV8 connected in parallel. The duty offset circuit 161 receives the internal clock signal LCLK1 and generates an internal clock signal LCLK2. Since these clocked inverters have the same circuit configuration, the configuration of the clocked inverter CV1 will be described as a representative here. The clocked inverter CV1 includes P-channel MOS transistors MP11 and MP12 connected in series in this order between a power supply wiring VL supplied with an internal potential VPERI and a power supply wiring SL supplied with a ground potential VSS, and an N-channel type. It is composed of MOS transistors MN12 and MN11.

  The gate electrodes of the transistors MP12 and MN12 are connected in common and constitute an input node n1 to which the internal clock signal LCLK1A is supplied. The internal clock signal LCLK1A is a signal obtained by inverting the internal clock signal LCLK1 by the inverter circuit INV. The drains of the transistors MP12 and MN12 are connected in common and constitute an output node n2 from which the internal clock signal PCLK1 is output.

  On the other hand, a control signal P1 which is a part of the offset signal OF is supplied to the gate electrode of the transistor MP11. Thereby, when the control signal P1 is activated to the low level, the clocked inverter CV1 can pull up the output node n2 based on the level of the input node n1. Conversely, when the control signal P1 is deactivated to a high level, the clocked inverter CV1 cannot pull up the output node n2. Thus, the transistors MP11 and MP12 connected in series constitute a pull-up circuit UP that is selectively activated by the control signal P1.

  Similarly, a control signal N1 that is a part of the offset signal OF is supplied to the gate electrode of the transistor MN11. Thereby, when the control signal N1 is activated to the high level, the clocked inverter CV1 can pull down the output node n2 based on the level of the input node n1. Conversely, when the control signal N1 is inactivated to a low level, the clocked inverter CV1 cannot pull down the output node n2. In this way, the transistors MN11 and MN12 connected in series constitute a pull-down circuit DN that is selectively activated by the control signal N1.

  Thus, the clocked inverter CV1 can control the pull-up circuit UP and the pull-down circuit DN independently of each other. This is different from a general clocked inverter.

  Other clocked inverters CV2, CV4, and CV8 also have the same circuit configuration as the clocked inverter CV1 described above except that the corresponding control signals are input.

  Here, the driving ability of the clocked inverters CV1, CV2, CV4, and CV8 is weighted by a power of 2. Specifically, assuming that the drive capability of the clocked inverter CV1 is 1DC, the drive capabilities of the clocked inverters CV2, CV4, and CV8 are 2DC, 4DC, and 8DC, respectively. Therefore, the pull-up capability can be controlled in 16 stages (0DC to 15DC) based on the control signals P1, P2, P4, and P8, and the pull-down capability can be set to 16 based on the control signals N1, N2, N4, and N8. It can be controlled in stages (0DC to 15DC).

  The second duty offset circuit 181 has a similar circuit configuration, and the duty ratio of the internal clock signal LCLK3 can be offset in multiple stages based on the duty detection signal D2. The duty correction circuit 150 also has a circuit configuration similar to that of the duty offset circuit 161 shown in FIG. 3, and changes the duty ratio of the internal clock signal PCLK1 in multiple steps based on the duty control signal D0. Can do.

  FIG. 4 is a flowchart for explaining the duty correction operation by the DLL circuit 100.

  The duty correction operation by the DLL circuit 100 is performed as follows. First, the duty detection signal D1 is generated by detecting the duty ratio of the internal clock signal LCLK2 using the first duty detection circuit 162 in a state where the offset operation by the duty offset circuit 161 is not performed (step S1). In this case, since the offset operation by the duty offset circuit 161 is not performed, the duty ratio of the internal clock signal LCLK2 is equal to the duty ratio of the internal clock signal LCLK1. Thereby, the duty correction operation by the duty correction circuit 150 is performed, and the duty ratio of the internal clock signal LCLK1 is adjusted to about 50%.

  FIG. 5 is a waveform diagram showing an example of the duty ratio of the internal clock signals PCLK0, LCLK1, and LCLK, and shows a case where the offset amount by the duty offset circuit 161 is zero.

  In the example shown in FIG. 5, the duty ratio of the internal clock signal PCLK0 is about 30%, but the duty ratio is corrected by the duty correction circuit 150, and the duty ratio of the internal clock signal LCLK1 is adjusted to about 50%. . However, the duty ratio shifts as it propagates through the clock tree 114. In the example shown in FIG. 5, the duty ratio of the internal clock signal LCLK output from the clock tree 114 is changed to about 60%. That is, in this example, if the clock tree 114 is propagated, the duty ratio of the clock signal LCLK increases by about 10%.

  Next, the duty cycle detection signal D2 is generated by activating the offset detection circuit 180 (step S2). Specifically, first, the duty ratio of the internal clock signal LCLK3 is detected using the second duty detection circuit 182 in a state where the offset operation by the duty offset circuit 181 is not performed. The duty detection signal D2 obtained as a result is fed back to the duty offset circuit 181. The duty offset circuit 181 generates the internal clock signal LCLK3 by offsetting the duty ratio of the internal clock signal LCLK based on the duty detection signal D2.

  FIG. 6 is a waveform diagram showing an example of the duty ratio of the internal clock signals LCLK and LCLK3.

  In the example shown in FIG. 6, the duty ratio of the internal clock signal LCLK is about 60%, and as a result of detection by the duty detection circuit 182, the duty ratio of the internal clock signal LCLK3 is adjusted to about 50%. That is, in the initial state, the offset amount by the duty offset circuit 181 is zero, and the duty ratio of the internal clock signal LCLK3 reflects the duty ratio of the internal clock signal LCLK as it is. The duty detection circuit 182 generates a duty detection signal D2 in response to the duty ratio of the internal clock signal LCLK3 exceeding 50%, and controls the duty offset circuit 181 to reduce the duty ratio of the internal clock signal LCLK3. Let By repeating such an operation, the duty ratio of the internal clock signal LCLK3 reaches about 50%.

  Then, the value of the duty detection signal D2 when the duty ratio of the internal clock signal LCLK3 reaches about 50% is reflected in the offset signal OF. The value of the offset signal OF is a value that cancels the offset amount by the duty offset circuit 181, and therefore corresponds to a value that increases the duty ratio by about 10% in this example. The offset signal OF having such a value is given to the duty offset circuit 161 (step S3).

  FIG. 7 is a waveform diagram for explaining the relationship between the internal clock signal LCLK1 and the internal clock signal LCLK2.

  In the example shown in FIG. 7, the offset signal OF is a value that increases the duty ratio by about 10%. For this reason, when the duty ratio of the internal clock signal LCLK1 is about 50%, the duty ratio of the internal clock signal LCLK2 is about Offset to 60%. In this case, in response to the duty ratio of internal clock signal LCLK2 exceeding 50%, duty detection circuit 162 performs feedback control so as to reduce the duty ratio of internal clock signal LCLK1.

  When such an operation is repeated, the duty ratio of the internal clock signal LCLK2 is controlled to about 50% as shown in FIG. In this case, the duty ratio of the internal clock signal LCLK1 is about 40%. As described above, when the offset operation is performed by the duty offset circuit 161, the duty ratio of the internal clock signal LCLK1 is controlled to a value offset from 50%.

  FIG. 8 is a waveform diagram showing an example of the duty ratio of the internal clock signals PCLK0, LCLK1, and LCLK, and shows a case where the duty offset circuit 161 performs an offset operation based on the offset signal OF.

  As shown in FIG. 8, when the duty offset circuit 161 performs an offset operation based on the offset signal OF, the duty ratio of the internal clock signal LCLK1 having a duty ratio of about 50% is reduced by about 10% as described above. , Adjusted to about 40%. When the internal clock signal LCLK1 having a duty ratio of about 40% is input to the clock tree 114, the duty ratio increases by about 10%, and the duty ratio of the output clock signal LCLK becomes about 50%.

  Thus, in this embodiment, the duty ratio of the clock signal LCLK output from the clock tree 114 can be adjusted to about 50%. In this embodiment, since the deviation of the duty ratio due to propagation through the clock tree 114 is detected and corrected within the semiconductor device 10, that is, within the semiconductor chip, an external tester is used. There is no need to perform an offset operation. For this reason, not only can the offset adjustment be performed with higher accuracy, but also the manufacturing cost can be reduced. Moreover, since the offset signal OF transmitted from the duty offset circuit 181 to the duty offset circuit 161 is a digital signal, the correct value can be easily maintained even when the transmission distance is long.

  Note that the duty correction operation shown in FIG. 4 may be executed every time when the semiconductor device 10 is turned on or reset, or may be executed only once in the manufacturing stage. The deviation of the duty ratio due to internal factors is predominantly due to process variations and is larger than the deviation due to power supply voltage fluctuations and clock frequency differences, so even if it is executed only once in the manufacturing stage, a high effect can be obtained. is there. When the operation shown in FIG. 4 is executed only once in the manufacturing stage, it is necessary to program the value of the offset signal OF in a nonvolatile memory element such as an antifuse element. As a result, the startup time is shortened as compared with the case where the process is executed every time the power is turned on or reset, and an increase in current consumption due to propagation of the clock signal LCLK through the clock tree 114 is also prevented.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Sense circuit 15 Amplifier circuit 20 Access control circuits 21-24 External terminal 25 Clock receiver 30 Data input / output circuit 30a Output circuit 31 Data terminal 32 Data strobe terminal 40 Power supply circuit 41, 42 power supply terminal 100 DLL circuit 110 delay line 111 coarse delay line 112 fine delay line 113 buffer 114 clock tree 120 replica circuit 130 phase determination circuit 140 delay line control circuit 150 duty correction circuit 161 first duty offset circuit 162 first duty Detection circuit 170 DCC control circuit 180 Offset detection circuit 181 Second duty offset circuit 182 Second duty detection circuit B L bit lines CV1, CV2, CV4, CV8 clocked inverter DN pull-down circuit INV inverter circuit MC memory cell MN11, MN12, MP11, MP12 transistor n1 input node n2 output node SA sense amplifier SL, VL power supply line UP pull-up circuit WL word line

Claims (12)

A clock tree through which the clock signal propagates;
A first duty detection circuit that generates a first duty detection signal by detecting a duty ratio of the clock signal input to the clock tree;
A second duty detection circuit that generates a second duty detection signal by detecting a duty ratio of the clock signal output from the clock tree;
And a duty correction circuit that adjusts a duty ratio of the clock signal based on the first and second duty detection signals.   The semiconductor device according to claim 1, further comprising a first duty offset circuit that offsets a duty ratio of the clock signal input to the first duty correction circuit.   The semiconductor device according to claim 2, wherein the first duty offset circuit offsets a duty ratio of the clock signal based on the second duty detection signal.   4. The semiconductor device according to claim 3, further comprising a second duty offset circuit that offsets a duty ratio of the clock signal input to the second duty correction circuit.   5. The semiconductor device according to claim 4, wherein the second duty offset circuit offsets the duty ratio of the clock signal so that the second duty detection signal indicates a predetermined value.   The semiconductor device according to claim 5, wherein the first duty offset circuit reflects an offset amount by the second duty offset circuit.   7. The semiconductor device according to claim 1, further comprising a delay line inserted between the duty correction circuit and the clock tree and delaying the clock signal. 8. A clock tree that receives a first clock signal and outputs a second clock signal;
An offset detection circuit that generates an offset signal by detecting a difference between a duty ratio of the second clock signal and a predetermined duty ratio;
A first duty offset circuit that generates a third clock signal by offsetting a duty ratio of the first clock signal based on the offset signal;
A semiconductor device, wherein the offset detection circuit and the first duty offset circuit are integrated on the same semiconductor chip. A first duty detection circuit that generates a first duty detection signal by detecting a duty ratio of the third clock signal;
The semiconductor device according to claim 8, further comprising a duty correction circuit that adjusts a duty ratio of the first clock signal based on the first duty detection signal.   The offset detection circuit generates a second duty detection signal by detecting a duty ratio of the second clock signal, and sets the duty ratio of the second clock signal to the second The semiconductor device according to claim 9, further comprising: a second duty offset circuit that performs offset based on the duty detection signal.   11. The offset detection circuit outputs the second duty detection signal as the offset signal when the duty ratio of the second clock signal reaches the predetermined duty ratio. Semiconductor device.   The semiconductor device according to claim 9, further comprising a delay line inserted between the duty correction circuit and the clock tree and delaying the first clock signal.

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