KR20060114234A - Circuit for generating delay locking clock and method for generating delay locking clock - Google Patents

Abstract

A circuit and a method for generating a delay locked clock are provided to generate a more stable delay locked clock, by preventing the period variation of a high level and a low level and the generation of glitch. In a synchronous semiconductor memory device outputting data in synchronization with a delay locked clock, a clock buffer buffers an external clock into an internal clock. An output buffer outputs data in synchronization with the delay locked clock. A phase comparator outputs a control signal by comparing the phases of the internal clock with a feedback clock, and outputs the control signal by synchronizing the control signal with another edge timing except a reference edge of the internal clock. A delay controller outputs a delay locked signal corresponding to the control signal. A delay line outputs a delay clock by delaying the internal clock as much as delay time responding to the delay locked signal. A delay model outputs the feedback signal by delaying the delayed clock outputted from the delay line as much as the modeling value of the delay value until the external clock is transferred to the output buffer. When the phases of two signals inputted to the phase comparator are equal, the delayed clock is outputted as the delay locked clock.

Description

CIRCUIT FOR GENERATING DELAY LOCKING CLOCK AND METHOD FOR GENERATING DELAY LOCKING CLOCK}

1 is a block diagram of a delay lock loop according to the prior art;

FIG. 2 is a circuit diagram showing a phase comparator shown in FIG.

3 is a circuit diagram showing the delay line shown in FIG.

4 is a circuit diagram showing the delay controller shown in FIG.

Fig. 5 is a circuit diagram showing the operation of the delay locked loop shown in Figs.

6 is a circuit diagram for generating a delay locked clock in accordance with a preferred embodiment of the present invention.

Fig. 7 is a waveform diagram showing the operation of the circuit diagram shown in Fig. 6;

Explanation of symbols on the main parts of the drawings

slo, sle: The write side movement signal of the clock to be delayed.

sro, sre: Left side shift signal of clock to be delayed.

Reg_1 ~ Reg_n: Delay Control Signal in Delay Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a circuit for generating a delayed clock for use in a semiconductor memory device and the like and a method of generating the same.

As the operation speed of a semiconductor memory device becomes faster and faster, a synchronous memory device that operates in synchronization with an input clock has been developed.

Recently, DDR memory devices that operate simultaneously with both the rising edge and the falling edge of an input clock to process data faster have been mainly used in a system.

The memory device processes data according to an internal clock buffered from an external clock, and an internal clock signal necessarily used internally by a clock input buffer that receives an external clock or a pad to which a clock signal is transmitted is externally There is a clock and a delay.

When data is output in accordance with an external clock and an internal clock in which a certain delay occurs, it is seen that the data is output with a constant delay time, rather than being synchronized with a clock.

In order to solve this problem, the memory device outputs data to the outside according to a delay locked clock which internally fixes a constant delay time.

When the memory device outputs data to the outside in synchronization with the delayed clock, the system is shown to output data to the outside in synchronization with the clock input to the memory device.

Fig. 1 is a block diagram of a delay locked loop which is generally used when a memory device outputs a delay locked clock.

Referring to FIG. 1, in order to output a delay locked clock, a memory device may include clock buffers 10a and 10b receiving externally input clock signals clk and clkb, and clock signals for a fixed fixed delay time. Delay lines 30a and 30b for delaying (clk, clkb) and outputting them, and clock signals rclk_dll and fclk_dll which are output from the delay lines 30a and 30b and transmitted through a clock signal line. An output buffer 90 for outputting the data signal Data transmitted from the memory core region to the outside, a clock buffer 20 for forming a loop for making a delayed clock signal, and a divider ( 40, a dummy delay line 60, a phase comparator 50, a delay controller 70, and a delay model 80.

The clock buffers 10a and 10b buffer the clock signals clk and clkb input from the outside and output them as internal clock signals rclk and fclk. The clock buffers 20 are the same as the clock buffers 10a and 10b. It is structured and provided to provide a reference clock with a delay locked loop circuit for generating a delay locked clock signal.

The divider 40 divides the reference clock inputted through the clock buffer 20 into the dummy delay line 60. The frequency of the externally input clock is divided by 1 / N (N is a positive number, usually 4 to 8). The main reason for the division is to reduce power consumption. By reducing the number of times each circuit (50, 60, 70, 80) of the delay locked loop is operated to reduce the power consumed by each circuit.

The delay model 80 is a circuit modeling a delay element until a clock is input from the outside of the memory device, transferred to the output buffer, and the data is output to the outside. Modeling the correct delay value depends on the performance of the delay lock loop. There are methods of modeling the path through which the clock signal is transmitted as it is, or reducing or simplifying the ratio. The actual delay model 80 models the clock buffers 10a and 10b, the output buffer 90 and the like, and the lines passing through the clocks.

A clock signal line is a path through which a delayed clock signal is transmitted from a delay line to an output buffer.

The output buffer 90 outputs the data signal Data to the outside in response to the delayed clock signals rclk_dll and fclk_dll.

When data is output in response to the delay-locked clock signals rclk_dll and fclk_dll, it is seen that the data is output according to the edge timing of the clock signals clk and clkb.

FIG. 2 is a circuit diagram illustrating the phase comparator shown in FIG. 1.

Referring to FIG. 2, the phase comparator 50 is a circuit for detecting a phase difference between a clock refclk input from a divider and a feedback clock fb output from the delay model 80. Since the phase of the clock refclk input from the divider 40 is compared, the frequency is lower than the clock clk input from the outside.

The phase comparator 50 controls signals delay and sro for controlling the delay controller 70 according to a comparison result of the comparator 51 and the comparator 51 comparing the phases of the two input clocks refclk and fb. and a control signal output unit 51 for outputting slo and sle.

FIG. 3 is a circuit diagram illustrating the delay line shown in FIG. 1.

Referring to FIG. 3, the delay lines 30a and 30b transmit the internal clocks rclk and fclk output from the clock buffers 10a and 10b to the delay lock signals Reg_n to Reg_1 output from the delay controller 70. It is a circuit that outputs after delaying only a certain time in response.

 As shown in FIG. 3, the delay lines 30a and 30b include a plurality of unit delays (Unit delay 1 to Unit delay n), and each unit delay signal (Reg_n) is output from the delay controller 70. It is activated or deactivated according to ~ Reg_1).

 Delay lines 30a and 30b exist for the rising clock and the falling clock, respectively, and this is to prevent the distortion of the duty as much as possible by processing the rising and falling edges of the clock separately.

The dummy delay line 60 has the same configuration as the delay lines 30a and 30b. The dummy delay line 60 responds to the delay lock signals Reg_n to Reg_1 output from the delay controller 70 with the reference clock refclk output from the divider. After a certain delay, the output will be delayed. The dummy delay line 60 is operated by receiving a reference clock refclk.

FIG. 4 is a circuit diagram illustrating the delay controller shown in FIG. 1.

Referring to FIG. 4, the delay controller 60 is a circuit block including a shifter register. The delay controller 60 receives four control signals sre, sro, slo, and sl from the phase comparator 50 in response to the delay lock signal. One of (Reg_n ~ Reg_1) is activated and printed.

FIG. 5 is a circuit diagram showing the operation of the delay locked loop shown in FIGS.

Hereinafter, a process and a problem of generating a delay locked clock according to the related art will be described with reference to FIGS. 1 to 5.

In the divider, the clock output from the clock buffer is divided at a predetermined ratio and output as a reference clock (refclk). Next, the dummy delay line 60 delays the reference clock refclk by a predetermined delay time and outputs the delayed reference clock.

Subsequently, the delay model 80 delays the delayed clock clk_out output from the dummy delay line 60 by the modeled internal circuit and then turns it into a feedback clock fb and outputs it to the phase comparator 50.

The phase comparator 50 compares the phases of the two clocks refclk and fb to output the control signals sre, sro, slo, and sl, and the delay controller 70 responds to the control signal to delay delay signals Reg_n to. Activate and print one of Reg_1).

The dummy delay line 60 and the delay lines 30a and 30b adjust the degree of delay according to the input delay fixing signals Reg_n to Reg_1.

If the after-signal signals slo and sle are activated and output according to the result of the phase comparison in the phase comparator 50, the edges of the delayed clock clk_out will be adjusted to move to the left-to-left side. When sre is active, the edge of the delayed clock (clk_out) will be adjusted to move towards the light accordingly.

The operation described above is compared until the edge timings of the two clocks refclk and fb input to the phase comparator 50 are the same, and when the two clocks refclk and fb become the same, the control signal is no longer activated and output. Not done.

At this time, the final phase is fixed, and the delayed clock signals rclk_dll and fclk_dll, which are output to the delay lines 30a and 30b, are used by the output buffer 90 to output data to the outside. )

There are four control signals (slo, sle, sro, sre) output from the phase comparator. These signals are enabled or disabled in synchronization with the rising edge of the reference clock refclk.

The control signals slo, sle, sro, sre eventually play a role of activating a selected one of a plurality of unit delays provided in the dummy delay line 60.

However, when the control signals slo, sle, sro, and sre are enabled or disabled in synchronization with the rising edge of the reference clock refclk, a plurality of unit delays included in the delay line are enabled / disabled. In the dummy delay line, the timing is not matched between the input reference clock (refclk) and the delay lock signal (Reg_n ~ Reg_1) because the timing for making the delay lock signal (Reg_n ~ Reg_1) is not sufficient. , The high level section is distorted.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problem, and an object of the present invention is to provide a circuit and a method for generating a delayed clocked signal for preventing a glitch or a distorted waveform from being generated. It is done.

A synchronous semiconductor device for outputting data in synchronization with a delay locked clock, comprising: a clock buffer configured to output an external clock buffered to an internal clock; An output buffer for outputting data in synchronization with the delay locked clock; Compare the phase of the internal clock and the feedback clock and output a control signal corresponding thereto, and synchronize the control signal with the remaining edge timing other than the reference edge (edge having a reference timing for processing data) of the internal clock. A phase comparator for outputting; A delay controller for outputting a delay lock signal corresponding to the control signal; A delay line for outputting the internal clock as a delayed clock delayed by a delay time in response to the delay lock signal; And a delay model for outputting the delayed clock outputted from the delay line as the feedback signal by delaying the delayed value until the external clock is transferred to the output buffer as a modeled value. Provided is a semiconductor device for outputting the delayed clock when the two signals to be substantially equal in phase to the delayed clock.

The present invention also provides a method of driving a semiconductor device for outputting internal data to the outside in synchronization with an external clock, the method comprising: buffering the external clock to generate an internal clock; Compare the phase of the internal clock and the feedback clock and output a control signal corresponding thereto, and synchronize the control signal with the remaining edge timing other than the reference edge (edge having a reference timing for processing data) of the internal clock. Outputting; Outputting a delayed clock obtained by shifting the edge timing of the internal clock by a delay time corresponding to the control signal; And outputting the delayed clock as the feedback signal by delaying the time that the external clock is delayed in the semiconductor device as a modeled time, and outputting the delayed clock when the phase of the internal clock and the feedback clock are substantially the same. A method of driving a semiconductor device that outputs the data to the outside in synchronization with a clock is provided.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

Fig. 6 is a circuit diagram for generating a delay locked clock according to a preferred embodiment of the present invention, in particular a circuit diagram showing a phase comparator.

The semiconductor device according to the present embodiment basically uses each block for generating the delay locked clock shown in FIG. These configurations are referred to FIG. 1, and the changed phase comparators are shown in detail in FIG. For reference, the remaining blocks other than the phase comparator basically have the same configuration as the circuit shown in FIGS. 1 to 4.

Referring to FIG. 6, the semiconductor device according to the present exemplary embodiment includes a clock buffer for buffering and outputting an external clock to an internal clock to output data in synchronization with a delay locked clock, and in synchronization with the delay locked clock. An output buffer for outputting data and a phase of the internal clock and the feedback clock are compared and a control signal corresponding thereto is output, and the control signal is a reference edge of the internal clock (edge having a reference timing for processing data). A phase comparator for outputting in synchronization with the remaining edge timings, a delay controller for outputting a delay lock signal corresponding to the control signal, and delaying the internal clock by a delay time in response to the delay lock signal. A delay line for outputting a delayed clock and a delayed output from the delay line And a delay model for outputting the clock as the feedback signal by delaying the delay value until the external clock is transferred to the output buffer as a modeled value, and the phase of the two signals input to the phase comparator is substantially The delayed clock at the same time is output as the delay locked clock.

The phase comparator 50 synchronizes the reference edge of the internal clock refclk, inverts the comparator 51 for comparing the phases of the internal clock refclk and the feedback clock fb, and inverts the internal clock refclk. The control signal output unit 52a for synchronizing the output signal of the inverter I with the inverter I to be outputted with the output signal of the inverter I to output the control signals sre, sro, slo, and sl. It is provided.

In addition, the semiconductor device according to the present exemplary embodiment may further include an internal clock output from the clock buffer as a divided internal clock divided into predetermined periods, and then further include a divider for providing the phase comparator and the delay line. (See Figure 1)

In addition, the semiconductor device according to the present exemplary embodiment includes two clock buffers for transferring a clock input from the outside, two delay lines, a clock buffer for outputting a delayed clock, and a dummy delay line. .

FIG. 7 is a waveform diagram showing the operation of the circuit diagram shown in FIG. Hereinafter, a method of generating a delay locked clock by the semiconductor memory device according to the present exemplary embodiment will be described with reference to FIGS. 6 and 6.

First, an internal clock is generated by buffering an externally input clock, and the generated internal clock is compared with a feedback clock fb in a phase comparator.

The comparator 51 of the phase comparator 50 compares the phase of the internal clock refclk and the feedback clock fb, and outputs a control signal according to the result from the control signal output unit 52a. The control signals sre, sro, slo, and sl are output in synchronization with the internal clock refclk inverted by I).

Therefore, as shown in FIG. 7, the control signals sre, sro, slo, and sle are output in synchronization with the polling edge of the internal clock refclk.

The polling edge of the internal clock (refclk) is not the reference edge of the internal clock (the edge having the reference timing for processing data), and the remaining edges are synchronized with this timing so that the control signals (sre, sro, slo, sl) are delayed. It is output to the controller.

The delay controller activates one of a plurality of delayed fixed signals Reg_1 to Reg_n in response to the control signals sre, sro, slo, and sl to output the dummy delay lines.

The dummy delay line outputs a delayed clock (clk_out) in which an internal clock (refclk) is delayed by a delayed fixed delay corresponding to a delayed fixed signal selectively activated among the plurality of delayed fixed signals (Reg_1 to Reg_n).

The phase comparator compares the internal clock and the feedback clock until the phase is substantially the same, and the delayed clock (clk_out) outputted when the internal clock and the feedback clock are the same phase becomes the delayed clock, and outputs the data from the output buffer. It will be a reference signal to be output.

The feedback signal is a signal from which a delayed clock (clk_out) output from the dummy delay line passes the delay model.

Therefore, the fact that the phase of the internal clock and the feedback clock input to the phase comparator is substantially the same means that the phase of the signal passing through the dummy delay line and the delay model and the signal that is not the same coincide by one period.

After all, to find the delay locked clock means to find the rest of the time delayed by the clock buffer, the output buffer, and the clock transmission path in one cycle of the clock, and if the delay line delays by the found time, In this section, the internal clock is delayed in one cycle.

In this case, the phase comparators are compared using a divided clock to reduce the amount of current consumed each time.

Meanwhile, the timing at which the control signal is output from the phase comparator is output at a timing opposite to the falling edge of the internal clock (refclk), that is, the reference timing at which data is output. The timing at which Reg_n) is output is allowed, which causes the delay line to delay and output the input clock in response to delay input signals Reg_1 to Reg_n already input.

As shown in FIG. 7, when the control signals slo and sl are generated at the falling edges of the internal clock signal, and the delay lock signals Reg_1 to Reg_n are output in response thereto, a plurality of units inside the delay line. The signal output from the delay removes glitches. Therefore, the final clock output from the delay line can be output as a stable waveform.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, when the delayed clock is generated, a glitch is generated or a change in the interval between the high level and the low level can be prevented, so that a more stable delayed clock can be generated.

Therefore, when the delayed clock is generated according to the present invention, data input and output of the semiconductor device can be more stably performed.

Claims (7)

A synchronous semiconductor device for outputting data in synchronization with a delay locked clock, A clock buffer for buffering and outputting the external clock to the internal clock; An output buffer for outputting data in synchronization with the delay locked clock; Compare the phase of the internal clock and the feedback clock and output a control signal corresponding thereto, and synchronize the control signal with the remaining edge timing other than the reference edge (edge having a reference timing for processing data) of the internal clock. A phase comparator for outputting; A delay controller for outputting a delay lock signal corresponding to the control signal; A delay line for outputting the internal clock as a delayed clock delayed by a delay time in response to the delay lock signal; And And a delay model for outputting the delayed clock output from the delay line as the feedback signal by delaying the delay value until the external clock is transferred to the output buffer as a modeled value. And output the delayed clock as the delay locked clock when the phases of two signals input to the phase comparator are substantially the same. The method of claim 1, The phase comparator A comparison unit configured to compare phases of the internal clock and the feedback clock in synchronization with a reference edge of the internal clock; An inverter for inverting and outputting the internal clock; And And a control signal output section for synchronizing the result signal of the comparator with an output signal of the inverter and outputting the control signal as the control signal. The method of claim 2, And a divider for generating an internal clock output from the clock buffer as a divided internal clock divided by a predetermined period and then providing the internal clock to the phase comparator and a delay line. The method of claim 3, wherein First and second clock buffers for data access for receiving a first external clock and a second external clock inverting the first external clock respectively and outputting a first internal clock and a second internal clock; And According to the control of the delay lock signal output from the delay controller, a delay fixed clock for the rising data for delaying the first internal clock and the second internal clock output from the first and second clock buffers for a predetermined time; And first and second delay lines for data access for outputting a delay locked clock for polling data. And the output buffer outputs data input in synchronization with the delay locked clock for the rising data and the delay locked clock for the falling data. A driving method of a semiconductor device for outputting internal data to the outside in synchronization with an external clock, Buffering the external clock to generate an internal clock; Compare the phase of the internal clock and the feedback clock and output a control signal corresponding thereto, and synchronize the control signal with the remaining edge timing other than the reference edge (edge having a reference timing for processing data) of the internal clock. Outputting; Outputting a delayed clock obtained by shifting the edge timing of the internal clock by a delay time corresponding to the control signal; And Outputting the delayed clock as the feedback signal by delaying the time that the external clock is delayed inside the semiconductor device by a modeling time; And transmitting the data to the outside in synchronization with the delayed clock when the phases of the internal clock and the feedback clock are substantially the same. The method of claim 5, And comparing the phases of the internal clock and the feedback clock by using a divided internal clock in which the internal clock is divided at a predetermined period. The method of claim 6, And a divided internal clock in which the internal clock is divided at predetermined periods in the step of outputting a delayed clock which shifts the edge timing of the internal clock.

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