JP6582502B2 - Integrated circuit and transmission circuit - Google Patents

Description

  The present invention relates to an integrated circuit and a transmission circuit.

  As a data transfer method between integrated circuits, serial data transmission is known in which parallel data including a plurality of bits is converted into serial data and transmitted. An integrated circuit mounted on an information processing apparatus such as a server includes a transmission circuit that transmits serial data via a plurality of transmission paths (hereinafter also referred to as lanes). This type of integrated circuit has a processing circuit that outputs a plurality of parallel data to a transmission circuit.

  The transmission circuit includes a plurality of transmission units provided corresponding to the plurality of lanes, and a clock generation unit that supplies a clock to the plurality of transmission units. The clock generation unit generates a processing clock synchronized with the parallel data and a transmission clock synchronized with the serial data, and supplies the generated processing clock and transmission clock to the plurality of transmission units.

  Each transmission unit receives parallel data synchronized with the processing clock from the processing circuit, and converts the parallel data received from the processing circuit into serial data. Each transmission unit transmits serial data to the integrated circuit on the reception side in synchronization with the transmission clock via the corresponding lane. As a result, the plurality of serial data are transmitted via the plurality of lanes. In this type of transmission circuit, measures are taken to reduce the difference in skew between the lanes (shift in timing at which signals such as clock and data arrive).

  For example, by comparing the phase of the frequency-divided clock obtained by dividing the frequency of the transmission clock used when transmitting serial data with the processing clock used when receiving parallel data, transmission that aligns the skew between lanes. A circuit has been proposed (see, for example, Patent Document 1). Each transmission unit of the transmission circuit divides the frequency of the transmission clock to generate a divided clock, and aligns the phase of the divided clock with the phase of the processing clock. Each transmission unit converts parallel data into serial data using the divided clock, processing clock, and transmission clock.

JP 2013-34087 A

  By the way, as the number of lanes increases, the number of transmission units to which processing clocks are distributed increases, so that the wander (fluctuation at a low frequency compared with jitter) that is the phase fluctuation of processing clocks received by the transmission unit is large. Become. For this reason, a FIFO (First-In First-Out) buffer or the like for absorbing the wander of the processing clock may be provided in each transmission unit. Each transmission unit absorbs wander by receiving parallel data from the processing circuit via a FIFO buffer or the like. Thereby, the influence of the wander of the processing clock supplied to each transmission unit is reduced. In the method of absorbing the wander of the processing clock with the buffer, the delay time of each transmitter increases by the time it takes for the data to pass through the buffer (the time from when the data is input to the buffer until it is output). To do.

  In one aspect, the integrated circuit and the transmission circuit of the present disclosure are intended to reduce the influence of clock wander in the transmission circuit without increasing the delay time of the transmission circuit.

  According to one aspect, the integrated circuit includes a processing circuit that generates data and a transmission circuit that transmits data generated by the processing circuit, and the transmission circuit supplies a first processing clock and a transmission clock. The clock generation unit receives a second processing clock and a transmission clock having a phase shifted from the phase of the first processing clock, receives data synchronized with the second processing clock from the processing circuit, and receives the received data as a transmission clock And a clock generation unit based on the comparison result of the phase comparison unit for comparing the phase of the second processing clock and the phase of the transmission clock, and the comparison result of the phase comparison unit. And a phase adjustment unit for adjusting the phase of the first processing clock.

  According to another aspect, a transmission circuit that transmits data generated by the processing circuit has a first processing clock and a clock generation unit that supplies the transmission clock, and a phase shifted from the phase of the first processing clock. A clock generation unit having a plurality of transmission units that receive the second processing clock and the transmission clock, receive data synchronized with the second processing clock from the processing circuit, and transmit the received data in synchronization with the transmission clock; Has a phase comparison unit that compares the phase of the second processing clock and the phase of the transmission clock, and a phase adjustment unit that adjusts the phase of the first processing clock based on the comparison result of the phase comparison unit. .

  The integrated circuit and the transmission circuit of the present disclosure can reduce the influence of clock wander in the transmission circuit without increasing the delay time of the transmission circuit.

1 is a diagram illustrating an embodiment of an integrated circuit and a transmission circuit. FIG. 6 illustrates another embodiment of an integrated circuit and a transmission circuit. It is a figure which shows an example of the transmission part shown in FIG. It is a figure which shows an example of operation | movement of the synthesizer shown in FIG. It is a figure which shows an example of the phase comparison part and phase adjustment part which were shown in FIG. It is a figure which shows an example of the resolution of the phase adjuster shown in FIG. FIG. 3 is a diagram illustrating an example of an operation of a clock generation unit illustrated in FIG. 2.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 illustrates one embodiment of an integrated circuit and a transmission circuit. The dashed arrows in FIG. 1 indicate the flow of information such as signals. An integrated circuit 10 shown in FIG. 1 is mounted on an information processing apparatus such as a server, and a plurality of data SD (SDa, SDb, SDc, SDd) is transferred to a plurality of transmission paths (lanes) 60 (60a, 60b, 60c, 60d). To other integrated circuits. The integrated circuit 10 includes a processing circuit 20 that generates data PD (PDa, PDb, PDc, PDd), and a transmission circuit 30 that transmits the data PD generated by the processing circuit 20 as data SD. For example, the data PD is parallel data including a plurality of bits, and the data SD is serial data.

  For example, the processing circuit 20 outputs a plurality of parallel data PD to a plurality of transmission units 40 (40a, 40b, 40c, 40d) in the transmission circuit 30 in response to a data transfer request to the integrated circuit 10.

  The transmission circuit 30 includes a plurality of transmission units 40 (40a, 40b, 40c, and 40d) provided corresponding to the plurality of lanes 60, and a clock that supplies the processing clock PCK and the transmission clock SCK to the plurality of transmission units 40, respectively. And a generation unit 50. For example, the frequency of the processing clock PCK corresponds to the frequency of the parallel data PD, and the frequency of the transmission clock SCK corresponds to the frequency of the serial data SD.

  Note that the processing clock PCK1 shown in FIG. 1 is the processing clock PCK output from the clock generation unit 50 (the processing clock PCK of the supply source). That is, the processing clock PCK1 is an example of a processing clock output from the clock generation unit 50. Further, the processing clock PCK2 shown in FIG. 1 is a processing clock PCK (supply destination processing clock PCK) transmitted from the clock generation unit 50 via the processing circuit 20 to the plurality of transmission units 40 and the like. For example, the processing clock PCK2 is the processing clock PCK in which the phase of the processing clock PCK1 is shifted. That is, the processing clock PCK1 is an example of a second processing clock in which the phase of the first processing clock is shifted.

  Each transmitter 40 receives the processing clock PCK2 and the transmission clock SCK from the clock generator 50. For example, the processing clock PCK <b> 2 is transferred from the clock generation unit 50 to each transmission unit 40 via the processing circuit 20. Each transmission unit 40 receives parallel data PD synchronized with the processing clock PCK2 from the processing circuit 20, and converts the parallel data PD received from the processing circuit 20 into serial data SD. Each transmitter 40 transmits the serial data SD to the receiving-side integrated circuit in synchronization with the transmission clock SCK via the corresponding lane 60. Thereby, the plurality of serial data SD are transmitted via the plurality of lanes 60, respectively.

  The clock generation unit 50 includes a clock output terminal 52 that outputs the processing clock PCK1, a phase comparison unit 54, and a phase adjustment unit 56. The clock generation unit 50 generates the processing clock PCK1 and the transmission clock SCK, and supplies the generated processing clock PCK1 and transmission clock SCK to the phase comparison unit 54 and the plurality of transmission units 40.

  For example, the clock generation unit 50 supplies the processing clock PCK to the phase comparison unit 54 and the plurality of transmission units 40 via the processing circuit 20. Thereby, the phase comparison unit 54 receives the processing clock PCK2 generated by the wander equivalent to the plurality of transmission units 40. Wander is a fluctuation in the phase of the clock (fluctuation at a lower frequency than jitter).

  The phases of a plurality of processing clocks PCK2 (processing clocks PCK1 whose processing clocks PCK1 are out of phase) received by the phase comparison unit 54 and the plurality of transmission units 40 are adjusted so as to be aligned with each other. For example, the processing clock PCK is supplied in parallel from the clock output terminal 52 of the clock generation unit 50 to the phase comparison unit 54 and the plurality of transmission units 40 via the tree-like clock wiring 22 branched in the processing circuit 20. Is done.

  The clock wiring 22 is an example of a branch wiring that branches the processing clock PCK into a plurality of parts and transmits one of the branched processing clocks PCK as the processing clock PCK2 to the phase comparison unit 54. For example, the clock wiring 22 is arranged with the wiring load from the clock output terminal 52 to the phase comparison unit 54 and the plurality of transmission units 40 aligned. As a result, the skews of the plurality of processing clocks PCK2 received by the phase comparison unit 54 and the plurality of transmission units 40 (shifts in timing at which signals such as clocks and data arrive) are aligned with each other. For example, the difference in skew between the plurality of processing clocks PCK2 received by the phase comparison unit 54 and the plurality of transmission units 40 is adjusted to a predetermined value or less.

  The phase comparator 54 compares the phase of the processing clock PCK2 (the processing clock PCK supplied from the clock output terminal 52 via the clock wiring 22) with the phase of the transmission clock SCK. Then, the phase comparison unit 54 outputs phase information PINF indicating the phase difference between the processing clock PCK2 and the transmission clock SCK to the phase adjustment unit 56.

  The phase adjustment unit 56 adjusts the phase of the processing clock PCK1 (processing clock PCK output from the clock generation unit 50) based on the comparison result in the phase comparison unit 54. For example, when the clock generation unit 50 starts supplying the processing clock PCK1 and the transmission clock SCK with stable frequencies, the phase adjustment unit 56 determines the phase difference indicated by the phase information PINF received from the phase comparison unit 54 as the initial phase difference. Remember as. Then, the phase adjustment unit 56 determines whether the phase difference between the processing clock PCK2 and the transmission clock SCK has changed from the initial phase difference based on the phase information PINF received from the phase comparison unit 54.

  A state where the phase difference between the processing clock PCK2 and the transmission clock SCK varies from the initial phase difference corresponds to a state where wander is generated in the processing clock PCK2. That is, the phase adjustment unit 56 determines whether wander has occurred in the processing clock PCK2 based on the phase information PINF received from the phase comparison unit 54.

  When determining that the phase difference between the processing clock PCK2 and the transmission clock SCK has changed from the initial phase difference, the phase adjustment unit 56 performs processing so that the phase difference between the processing clock PCK2 and the transmission clock SCK returns to the initial phase difference. The phase of the clock PCK1 is adjusted. Thereby, the phase difference between the processing clock PCK2 received by the phase comparator 54 and the transmission clock SCK is maintained at the initial phase difference.

  Note that the skews of the processing clocks PCK2 received by the phase comparison unit 54 are aligned with the skews of the plurality of processing clocks PCK2 received by the plurality of transmission units 40, respectively. Therefore, by maintaining the phase difference between the processing clock PCK2 received by the phase comparison unit 54 and the transmission clock SCK at the initial phase difference, the phase difference between the plurality of processing clocks PCK2 received by the plurality of transmission units 40 and the transmission clock SCK, respectively. Is maintained at the initial phase difference.

  In this way, the phase adjustment unit 56 adjusts the phase of the processing clock PCK1 so that the phase difference between the processing clock PCK2 and the transmission clock SCK returns to the initial phase difference even when wander occurs in the processing clock PCK2. Cancels the wander of the processing clock PCK2. That is, the phase adjustment unit 56 determines whether wander has occurred in the processing clock PCK2 based on the phase information PINF. If it is determined that wander has occurred in the processing clock PCK2, the phase adjustment unit 56 performs processing to cancel the wander of the processing clock PCK2. The phase of the clock PCK1 is adjusted. Thereby, each transmission unit 40 receives the processing clock PCK2 in which the generation of wander is suppressed.

  Therefore, the transmission circuit 30 can reduce the influence of the wander of the processing clock PCK2 without having a FIFO (First-In First-Out) buffer or the like for absorbing the wander of the processing clock PCK2. That is, the influence of the wander of the processing clock PCK2 in the transmission circuit 30 can be reduced without increasing the delay time of the transmission circuit 30. The delay time of the transmission circuit 30 is a time from when the transmission circuit 30 receives the parallel data PD to when the serial data SD is transmitted. Similarly, the delay time of the transmission unit 40 is the time from when the transmission unit 40 receives the parallel data PD until the serial data SD is transmitted.

  Here, for example, when the phase comparison unit 54 and the phase adjustment unit 56 are omitted from the clock generation unit 50, each transmission unit 40 receives the processing clock PCK2 generated by the wander. In this case, each transmission unit 40 includes a FIFO buffer or the like for absorbing the wander of the processing clock PCK2 in order to reduce the influence of the wander of the processing clock PCK2.

  For example, each transmission unit 40 absorbs wander by receiving parallel data PD from the processing circuit 20 via a buffer. When the buffer for absorbing the wander of the processing clock PCK2 holds two 32-bit parallel data PD (64-bit data), each transmission unit 40 can support wander less than 64 UI (Unit Interval). is there.

  In the method in which the wander of the processing clock PCK2 is absorbed by the buffer, the delay time of each transmitter 40 increases by the delay time generated in the buffer. Further, as the number of lanes increases, the wander of the processing clock PCK2 received by the transmission unit 40 increases, so the number of buffer stages (for example, the number of FIFO stages) for absorbing the wander of the processing clock PCK2 increases. That is, in the method in which the wander of the processing clock PCK2 is absorbed by the buffer, the delay time of each transmission unit 40 increases as the number of lanes increases.

  On the other hand, since each transmission unit 40 shown in FIG. 1 receives the processing clock PCK2 in which the generation of wander is suppressed, even in the configuration in which the buffer for absorbing the wander of the processing clock PCK2 is omitted, the transmission clock 40K The effect of wander can be reduced. As a result, the delay time of each transmitter 40 can be reduced by the delay time generated in the buffer, compared to the method in which the wander of the processing clock PCK2 is absorbed by the buffer. For example, the delay time of the transmission circuit 30 is equivalent to 64 UI compared to a configuration in which a wander of the processing clock PCK2 is absorbed using a buffer that holds two 32-bit parallel data PD (64-bit data). Can be reduced.

  Note that the configurations of the integrated circuit 10 and the transmission circuit 30 are not limited to the example shown in FIG. For example, the number of transmission units 40 may be two or three. Alternatively, the number of transmission units 40 may be five or more. The clock generation unit 50 may receive the transmission clock SCK from the outside.

  As described above, in the embodiment shown in FIG. 1, the influence of wander of the clock (processing clock PCK2) in the transmission circuit 30 can be reduced without increasing the delay time of the transmission circuit 30. Since the delay time of the transmission circuit 30 can be reduced, the latency of the integrated circuit 10 (the delay time from when the data transfer or the like is requested to the integrated circuit 10 until the request result is returned) is reduced. be able to. That is, the influence of the wander of the processing clock PCK2 can be reduced without increasing the latency of the integrated circuit 10.

  Further, even when the wander generated in the processing clock PCK increases as the number of the transmitting units 40 increases, each transmitting unit 40 receives the processing clock PCK2 in which the generation of wander is suppressed. For this reason, even when the number of transmission units 40 increases, the influence of the wander of the processing clock PCK2 can be reduced without increasing the delay time of the transmission circuit 30.

  FIG. 2 shows another embodiment of an integrated circuit and a transmission circuit. The same or similar elements as those described in FIG. 1 are denoted by the same or similar reference numerals, and detailed description thereof will be omitted. The dashed arrows in FIG. 2 indicate the flow of information such as signals. The integrated circuit 100 shown in FIG. 2 is mounted on an information processing apparatus such as a server, and a plurality of serial data SD (SDa, SDb, SDc, SDd) is passed through a plurality of lanes 600 (600a, 600b, 600c, 600d). Transfer to another integrated circuit. The integrated circuit 100 includes a processing circuit 200 that generates parallel data PD (PDa, PDb, PDc, PDd), and a transmission circuit 300 that converts the parallel data PD generated by the processing circuit 200 into serial data SD and transmits the serial data SD. Have.

  For example, the processing circuit 200 outputs a plurality of parallel data PD to a plurality of transmission units 400 (400a, 400b, 400c, 400d) in the transmission circuit 300 in response to a data transfer request to the integrated circuit 100.

  The transmission circuit 300 includes a plurality of transmission units 400 (400a, 400b, 400c, and 400d) provided corresponding to the plurality of lanes 600, and a clock that supplies the processing clock PCK and the transmission clock SCK to the plurality of transmission units 400. And a generation unit 500. Note that the processing clocks PCK1 and PCK2 shown in FIG. 2 are the supply source processing clock PCK and the supply destination processing clock PCK, respectively, as described in FIG. For example, the processing clock PCK2 is the processing clock PCK in which the phase of the processing clock PCK1 is shifted.

  Each transmission unit 400 receives the processing clock PCK2 and the transmission clock SCK from the clock generation unit 500. For example, the processing clock PCK2 is transferred from the clock generation unit 500 to each transmission unit 400 via the processing circuit 200. Each transmission unit 400 receives parallel data PD synchronized with the processing clock PCK2 from the processing circuit 200, and converts the parallel data PD received from the processing circuit 200 into serial data SD. Each transmitting unit 400 transmits serial data SD to the receiving-side integrated circuit via the corresponding lane 600 in synchronization with the transmission clock SCK. Thereby, the plurality of serial data SD are transmitted through the plurality of lanes 600, respectively. Details of the transmission unit 400 will be described with reference to FIG.

  The clock generation unit 500 includes a clock output terminal 520 that outputs a processing clock PCK1, a PLL (Phase Locked Loop) circuit 530, a phase comparison unit 540, and a phase adjustment unit 560. Then, the clock generation unit 500 supplies the processing clock PCK1 and the transmission clock SCK to the phase comparison unit 540 and the plurality of transmission units 400. For example, the clock generation unit 500 supplies the processing clock PCK to the phase comparison unit 540 and the plurality of transmission units 400 in parallel via the tree-like clock wiring 202 branched in the processing circuit 200.

  Before describing the PLL circuit 530, the phase comparison unit 540, and the phase adjustment unit 560, the clock wiring 202 connected to the clock output terminal 520 will be described.

  The clock wiring 202 is an example of a branch wiring that branches the processing clock PCK into a plurality of parts and transmits one of the branched processing clocks PCK to the phase comparison unit 540 as the processing clock PCK2. For example, the clock wiring 202 is connected to the phase comparison unit 540 and the plurality of transmission units 400 and branches the processing clock PCK output from the clock output terminal 520 into a plurality in the processing circuit 200. Then, the clock wiring 202 transmits the branched processing clock PCK as the processing clock PCK2 to the phase comparison unit 540 and the plurality of transmission units 400, respectively. Note that the clock wiring 202 is arranged with the wiring loads from the clock output terminal 520 to the phase comparison unit 540 and the plurality of transmission units 400 aligned.

  Thereby, the phases of the plurality of processing clocks PCK2 (the processing clocks PCK1 whose processing clocks PCK1 are out of phase) received by the phase comparison unit 540 and the plurality of transmission units 400 are adjusted so as to be aligned with each other. That is, the skews of the plurality of processing clocks PCK2 received by the phase comparison unit 540 and the plurality of transmission units 400 are aligned with each other.

  The clock wiring 202 includes a plurality of clock drivers 210-245 that shape the waveform of the processing clock PCK. In the example of FIG. 2, the clock drivers 210, 220, 221, 230, 232, and 234 shape the waveform of the processing clock PCK and branch the processing clock PCK in two directions. The clock drivers 231 and 241 are dummy clock drivers for aligning the skew of the processing clock PCK2 received by the phase comparison unit 540 with the skew of the processing clock PCK2 received by the plurality of transmission units 400. For example, by connecting the dummy clock driver 231 to the output of the clock driver 220, the load of the clock driver 220 (clock drivers 230 and 231) can be matched to the load of the clock driver 221 (clock drivers 232 and 234).

  Thereby, the amount of delay of the processing clock PCK generated by the clock driver 220 and the amount of delay of the processing clock PCK generated by the clock driver 221 can be made equal (or substantially equal) to each other. As a result, the skews of the plurality of processing clocks PCK2 received by the phase comparison unit 540 and the plurality of transmission units 400 are aligned with each other. For example, the skew difference between the plurality of processing clocks PCK2 received by the phase comparison unit 540 and the plurality of transmission units 400 is adjusted to a predetermined value or less.

  The PLL circuit 530 generates a transmission clock SCK based on a reference clock received from the outside. The PLL circuit 530 supplies the transmission clock SCK to the phase comparison unit 540 and the plurality of transmission units 400, and supplies the n-phase (n is an integer of 1 or more) transmission clock SCK-n to the phase adjustment unit 560. . The transmission clock SCK-n is, for example, a four-phase transmission clock SCK having phases of 0 °, 90 °, 180 °, and 270 °. The transmission clock SCK-n may be a transmission clock SCK other than four phases. For example, the transmission clock SCK-n may be an eight-phase transmission clock SCK having phases of 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 °.

  Further, the PLL circuit 530 receives the lock information LINF indicating that the frequency of the transmission clock SCK is stable when the frequency of the transmission clock SCK falls within a predetermined frequency range, and the phase comparison unit 540 and the phase adjustment. To the unit 560.

  The phase comparison unit 540 compares the phase of the processing clock PCK2 (the processing clock PCK supplied from the clock output terminal 520 via the tree-like clock wiring 202 and the like) with the phase of the transmission clock SCK. Then, the phase comparison unit 540 outputs phase information PINF indicating the phase difference between the processing clock PCK2 and the transmission clock SCK to the phase adjustment unit 560.

  The phase adjustment unit 560 adjusts the phase of the processing clock PCK1 (processing clock PCK output from the clock generation unit 50) based on the comparison result in the phase comparison unit 540. For example, when the phase adjustment unit 560 receives the lock information LINF indicating that the frequency of the transmission clock SCK is stable from the PLL circuit 530, the clock generation unit 500 supplies the processing clock PCK1 and the transmission clock SCK with stable frequencies. It is determined that it has started.

  Therefore, when receiving the lock information LINF indicating that the frequency of the transmission clock SCK is stable from the PLL circuit 530, the phase adjustment unit 560 determines the phase difference indicated by the phase information PINF received from the phase comparison unit 540 as the initial phase difference. Remember as. Then, phase adjustment unit 560 determines whether the phase difference between processing clock PCK2 and transmission clock SCK has changed from the initial phase difference based on phase information PINF received from phase comparison unit 540.

  When it is determined that the phase difference between the processing clock PCK2 and the transmission clock SCK has changed from the initial phase difference, the phase adjustment unit 560 performs processing so that the phase difference between the processing clock PCK2 and the transmission clock SCK returns to the initial phase difference. The phase of the clock PCK1 is adjusted. Thereby, the phase difference between the processing clock PCK2 received by the phase comparison unit 540 and the transmission clock SCK is maintained at the initial phase difference.

  Note that the skews of the processing clocks PCK2 received by the phase comparison unit 540 are aligned with the skews of the plurality of processing clocks PCK2 received by the plurality of transmission units 400, respectively. Accordingly, by maintaining the phase difference between the processing clock PCK2 received by the phase comparison unit 540 and the transmission clock SCK at the initial phase difference, the phase difference between the plurality of processing clocks PCK2 and the transmission clock SCK received by the plurality of transmission units 400, respectively. Is maintained at the initial phase difference.

  As described above, the phase adjustment unit 560 adjusts the phase of the processing clock PCK1 so that the phase difference between the processing clock PCK2 and the transmission clock SCK returns to the initial phase difference even when wander occurs in the processing clock PCK2. Cancels the wander of the processing clock PCK2. That is, the phase adjustment unit 560 determines whether wander has occurred in the processing clock PCK2, based on the phase information PINF. If it is determined that wander has occurred in the processing clock PCK2, the phase adjustment unit 560 performs processing to cancel the wander of the processing clock PCK2. The phase of the clock PCK1 is adjusted. Thereby, each transmission unit 400 receives the processing clock PCK2 in which the generation of wander is suppressed.

  Therefore, the transmission circuit 300 can reduce the influence of the wander of the processing clock PCK2 without having a FIFO buffer or the like for absorbing the wander of the processing clock PCK2. That is, the influence of the wander of the processing clock PCK2 in the transmission circuit 300 can be reduced without increasing the delay time of the transmission circuit 300.

  Note that the configurations of the integrated circuit 100 and the transmission circuit 300 are not limited to the example shown in FIG. For example, the number of transmission units 400 may be two or three. Alternatively, the number of transmission units 400 may be five or more. A part of the plurality of clock drivers 210-245 for shaping the waveform of the processing clock PCK may be arranged outside the processing circuit 200. For example, the dummy clock driver 241 may be disposed in the transmission circuit 300.

  FIG. 3 shows an example of the transmission unit 400 shown in FIG. FIG. 3 shows an example of the transmission unit 400 when the frequency of the transmission clock SCK is eight times the frequency of the processing clock PCK. The dashed arrows in FIG. 3 indicate the flow of information such as signals.

  The transmission unit 400 includes a synthesizer 410, a multiplexer unit 470 that converts parallel data into serial data, and an output buffer 480. Hereinafter, the multiplexer unit 470 is also referred to as a MUX (multiplexer) unit 470.

  The synthesizer 410 receives the processing clock PCK2 from the clock generation unit 500 via the processing circuit 200, and receives the transmission clock SCK from the clock generation unit 500. The synthesizer 410 generates a reception clock RCK used when the MUX unit 470 receives the data PD based on the processing clock PCK2 and the transmission clock SCK, and outputs the generated reception clock RCK to the MUX unit 470. For example, the synthesizer 410 includes a frequency divider 420, a phase generator 430, flip-flops 440-447, a selection information generator 450, and a clock selection unit 460.

  The circuit including the frequency divider 420, the phase generator 430, the flip-flops 440-447, and the selection information generator 450 compares the phase of the processing clock PCK2 with the phase of the transmission clock SCK using a plurality of frequency-divided clocks DCKs. This is an example of a second phase comparison unit. The clock selection unit 460 is an example of a clock selection unit that selects the reception clock RCK from the plurality of divided clocks DCKs based on the comparison result in the second phase comparison unit.

  For example, the frequency divider 420 divides the frequency of the transmission clock SCK received from the clock generation unit 500 by 8 to generate a divided clock DCKs0. The frequency-divided clock DCKs0 is generated so that the frequency is the same (or almost the same) as the frequency of the processing clock PCK. Then, the frequency divider 420 outputs the frequency-divided clock DCKs0 to the phase generator 430.

  The phase generator 430 receives the transmission clock SCK from the clock generation unit 500 and receives the divided clock DCKs0 from the frequency divider 420. Then, the phase generator 430 generates an eight-phase divided clock DCKs (DCKs0, DCKs45, DCKs90, DCKs135, DCKs180, DCKs225, DCKs270, DCKs315) using the transmission clock SCK and the divided clock DCKs0.

  The number at the end of the sign of each frequency-divided clock DCKs (for example, 45 of DCKs45) indicates the phase of each frequency-divided clock DCKs when the phase of frequency-divided clock DCKs0 is 0 °. For example, the divided clocks DCKs0, DCKs45, DCKs90, and DCKs135 are divided clocks DCKs having phases of 0 °, 45 °, 90 °, and 135 °, respectively. The frequency-divided clocks DCKs180, DCKs225, DCKs270, and DCKs315 are frequency-divided clocks DCKs having phases of 180 °, 225 °, 270 °, and 315 °, respectively.

  The 8-phase divided clocks DCKs are transferred to the flip-flops 440 to 447 and the clock selection unit 460. For example, the phase generator 430 outputs eight-phase frequency-divided clocks DCKs0, DCKs45, DCKs90, DCKs135, DCKs180, DCKs225, DCKs270, and DCKs315 to the clock selection unit 460. The phase generator 430 outputs 8-phase frequency-divided clocks DCKs0, DCKs45, DCKs90, DCKs135, DCKs180, DCKs225, DCKs270, and DCKs315 to the flip-flops 440-447, respectively.

  The flip-flop 440 receives the divided clock DCKs0 at the clock terminal and the processing clock PCK2 at the data input terminal D. Then, the flip-flop 440 outputs the processing clock PCK2 received at the data input terminal D as comparison information PSs0 to the selection information generator 450 from the data output terminal Q in synchronization with the divided clock DCKs0 received at the clock terminal. For example, the flip-flop 440 outputs the logical level (logical value) of the processing clock PCK2 when the frequency-divided clock DCKs0 rises as comparison information PSs0 to the selection information generator 450. That is, the flip-flop 440 determines whether the phase of the processing clock PCK2 is delayed (or advanced) with respect to the phase of the divided clock DCKs0.

  Therefore, the comparison information PSs0 corresponds to information indicating a comparison result between the phase of the divided clock DCKs0 and the phase of the processing clock PCK2. Note that the number at the end of the code of the comparison information PSs (for example, 0 of PSs0) corresponds to the number at the end of the code of the divided clock DCKs. For example, the comparison information PSs45 indicates a comparison result between the phase of the divided clock DCKs45 and the phase of the processing clock PCK2.

  The operations of the flip-flops 441 to 447 are the same as those of the flip-flop 440, and the numbers 0 at the end of the signs of the comparison information PSs and the divided clock DCKs are changed to 45, 90, 135, 180, 225, 270, and 315, respectively. It will be explained by re-reading. For example, the flip-flop 441 outputs the processing clock PCK2 received at the data input terminal D as the comparison information PSs45 and outputs it from the data output terminal Q to the selection information generator 450 in synchronization with the divided clock DCKs45 received at the clock terminal.

  For example, as shown in FIG. 4, when the phase of the processing clock PCK2 is delayed from the divided clock DCKs45 and advanced from the divided clock DCKs90, the comparison information PSs45 and PSs90 have logical values 0 and 1, respectively.

  The selection information generator 450 receives the comparison information PSs0, PSs45, PSs90, PSs135, PSs180, PSs225, PSs270, and PSs315 from the flip-flops 440-447, respectively. Then, the selection information generator 450 generates selection information SINF based on the comparison information PSs received from the flip-flops 440-447. In the example of FIG. 3, since one divided clock DCKs is selected from the eight-phase divided clocks DCKs, the number of bits of the selection information SINF is 3 bits or more. Hereinafter, description will be made assuming that the number of bits of the selection information SINF is 3 bits.

  The selection information SINF is obtained when the phase range is divided by 0 ° (360 °), 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° with reference to the phase of the divided clock DCKs0. , Indicates in which phase range the phase of the processing clock PCK2 exists. That is, the selection information SINF corresponds to information indicating a comparison result (phase difference) between the phase of the processing clock PCK2 and the phase of the transmission clock SCK.

  For example, the selection information generator 450 selects the selection information when the comparison information PSs0, PSs45, PSs90, PSs135, PSs180, PSs225, PSs270, and PSs315 are logical values 0, 0, 1, 1, 1, 1, 0, 0, respectively. Set the value of SINF to 2. When the value of the selection information SINF is 2, the phase of the processing clock PCK2 exists in the range of 45 ° to 90 °.

  Based on the selection information SINF, the clock selection unit 460 selects one of the divided clocks DCKs0, DCKs45, DCKs90, DCKs135, DCKs180, DCKs225, DCKs270, and DCKs315. Then, the clock selection unit 460 outputs the selected divided clock DCKs to the MUX unit 470 as the reception clock RCK.

  For example, when the phase of the processing clock PCK2 is greater than (i−1) × 45 ° and equal to or less than i × 45 ° (i is an integer from 0 to 7), for example, the clock selection unit 460 increases the phase by i × 45 ° The peripheral clock DCKs is selected as the reception clock RCK. Note that i corresponds to the value of the selection information SINF. For example, when the value of the selection information SINF is 2 (when the phase of the processing clock PCK2 is greater than 45 ° and 90 ° or less), the clock selection unit 460 outputs the divided clock DCKs90 to the MUX unit 470 as the reception clock RCK. .

  The MUX unit 470 receives the reception clock RCK, the transmission clock SCK, and the parallel data PD from the synthesizer 410, the clock generation unit 500, and the processing circuit 200, respectively, and outputs the serial data SD to the output buffer 480 differentially. The serial data SD (N) is serial data SD obtained by inverting the serial data SD (P). For example, the MUX unit 470 receives the parallel data PD synchronized with the processing clock PCK2 in synchronization with the reception clock RCK, and converts the parallel data PD into serial data SD.

  Then, the MUX unit 470 differentially outputs the converted serial data SD to the output buffer 480 in synchronization with the transmission clock SCK. The output buffer 480 transmits the differential serial data SD (SD (P), SD (N)) received from the MUX unit 470 to the integrated circuit on the receiving side. In this way, the MUX unit 470 transmits the differential serial data SD via the output buffer 480 in synchronization with the transmission clock SCK.

  In addition, the structure of the transmission part 400 is not limited to the example shown in FIG. For example, the synthesizer 410 includes a circuit that combines a frequency divider 420 and a phase generator 430 (a circuit that generates a plurality of divided clocks DCKs having different phases when dividing the frequency of the transmission clock SCK). May be.

  FIG. 4 shows an example of the operation of the synthesizer 410 shown in FIG. FIG. 4 shows the operation of the synthesizer 410 when the phase of the processing clock PCK2 is greater than 45 ° and less than 90 ° when the phase of the divided clock DCKs0 is used as a reference.

  The flip-flop 440 outputs the logical value 0 of the processing clock PCK2 when the frequency-divided clock DCKs0 rises to the selection information generator 450 as comparison information PSs0. The flip-flop 441 outputs the logical value 0 of the processing clock PCK2 when the divided clock DCKs45 rises to the selection information generator 450 as comparison information PSs45. The flip-flop 442 outputs the logical value 1 of the processing clock PCK2 when the divided clock DCKs90 rises to the selection information generator 450 as comparison information PSs90. The flip-flop 443 outputs the logical value 1 of the processing clock PCK2 when the divided clock DCKs135 rises to the selection information generator 450 as comparison information PSs135.

  The flip-flop 444 outputs the logical value 1 of the processing clock PCK2 when the frequency-divided clock DCKs180 rises to the selection information generator 450 as comparison information PSs180. The flip-flop 445 outputs the logical value 1 of the processing clock PCK2 when the frequency-divided clock DCKs225 rises to the selection information generator 450 as the comparison information PSs225. The flip-flop 446 outputs the logical value 0 of the processing clock PCK2 when the frequency-divided clock DCKs270 rises to the selection information generator 450 as comparison information PSs270. The flip-flop 447 outputs the logical value 0 of the processing clock PCK2 when the frequency-divided clock DCKs315 rises to the selection information generator 450 as comparison information PSs315.

  The selection information generator 450 is a place where the logical value switches from 0 to 1 when the logical value of the comparison information PSs is scanned in the order of the comparison information PSs0, PSs45, PSs90, PSs135, PSs180, PSs225, PSs270, PSs315, and PSs0. Is detected. In the example of FIG. 3, since the logical value of the comparison information PSs45 is 0 and the logical value of the comparison information PSs90 is 1, the selection information generator 450 uses the comparison information PSs90 as a place where the logical value switches from 0 to 1. To detect. In this case, the rising edge of the processing clock PCK2 exists between the rising edge of the divided clock DCKs45 and the rising edge of the divided clock DCKs90. Therefore, the selection information generator 450 sets the selection information SINF to a value (= 2) indicating the divided clock DCKs90 corresponding to the comparison information PSs90.

  The clock selection unit 460 selects the divided clock DCKs corresponding to the value of the selection information SINF as the reception clock RCK. For example, when the value of the selection information SINF is 2, the clock selection unit 460 selects the divided clock DCKs90 and outputs the selected divided clock DCKs90 to the MUX unit 470 as the reception clock RCK.

  As described above, when the phase of the processing clock PCK2 is greater than (i−1) × 45 ° and equal to or less than i × 45 ° (i is an integer from 0 to 7), the clock selection unit 460 has a phase of i × 45 °. The divided clock DCKs is output to the MUX unit 470 as the reception clock RCK. Note that i corresponds to the value of the selection information SINF. For example, when the value of the selection information SINF is 0 (when the phase of the processing clock PCK2 is greater than −45 ° (315 °) and less than or equal to 0 ° (360 °)), the clock selection unit 460 receives the divided clock DCKs0. The clock RCK is output to the MUX unit 470.

  The operation of synthesizer 410 is not limited to the example shown in FIG. For example, when the phase of the processing clock PCK2 is not less than i × 45 ° and less than (i + 1) × 45 ° (i is an integer from 0 to 7), the synthesizer 410 generates the divided clock DCKs having a phase of i × 45 °. The reception clock RCK may be selected. In this case, when the phase of the processing clock PCK2 is 0 ° or more and less than 45 ° (i = 0), the divided clock DCKs0 is selected as the reception clock RCK.

  Alternatively, the synthesizer 410 may select the divided clock DCKs having a phase obtained by adding a predetermined offset to the phase range in which the phase of the processing clock PCK2 exists as the reception clock RCK. For example, when the phase of the processing clock PCK2 is not less than i × 45 ° and less than (i + 1) × 45 ° (i is an integer from 0 to 7), the synthesizer 410 has a divided clock having a phase of (i + 4) × 45 °. DCKs may be selected as the reception clock RCK.

  FIG. 5 shows an example of the phase comparison unit 540 and the phase adjustment unit 560 shown in FIG. Note that the phase comparison unit 540 illustrated in FIG. 5 is an example of the case where the frequency of the transmission clock SCK is eight times the frequency of the processing clock PCK. The dashed arrows in FIG. 5 indicate the flow of information such as signals. The meanings of the numbers at the end of the signs of the divided clock DCKp and the comparison information PSp shown in FIG. 5 are the same as or similar to the meanings of the numbers at the end of the signs of the divided clock DCKs and the comparison information PSs shown in FIG. .

  The phase comparison unit 540 receives the processing clock PCK2 from the clock output terminal 520 of the clock generation unit 500 via the processing circuit 200, and receives the transmission clock SCK from the PLL circuit 530. In addition, the phase comparison unit 540 receives, from the PLL circuit 530, lock information LINF indicating that the frequency of the transmission clock SCK is stable when the transmission clock SCK has shifted to a locked state in which the frequency falls within a predetermined frequency range. Then, the phase comparison unit 540 outputs phase information PINF indicating the phase difference between the processing clock PCK2 and the transmission clock SCK to the phase adjustment unit 560. For example, the phase comparison unit 540 includes a frequency divider 542, a phase generator 544, flip-flops 550-557, and a phase information generator 558.

  The operations of frequency divider 542, phase generator 544, and flip-flops 550-557 are the same as or similar to those of frequency divider 420, phase generator 430, and flip-flops 440-447 shown in FIG. The operations of the frequency divider 542, the phase generator 544, and the flip-flop 550-557 are obtained by replacing the codes 420, 430, 440-447, PSs, and DCKs with the codes 542, 544, 550-557, PSp, and DCKp, respectively. Explained.

  For example, the frequency divider 542 divides the frequency of the transmission clock SCK received from the clock generation unit 500 by 8 to generate the divided clock DCKp0. The phase generator 544 receives the transmission clock SCK from the PLL circuit 530 and receives the frequency-divided clock DCKp0 from the frequency divider 542. Then, the phase generator 544 generates an eight-phase divided clock DCKp (DCKp0, DCKp45, DCKp90, DCKp135, DCKp180, DCKp225, DCKp270, DCKp315) using the transmission clock SCK and the divided clock DCKp0. The phase generator 544 outputs 8-phase frequency-divided clocks DCKp0, DCKp45, DCKp90, DCKp135, DCKp180, DCKp225, DCKp270, and DCKp315 to the flip-flops 550-557, respectively.

  Flip-flops 550-557 receive frequency-divided clocks DCKp0, DCKp45, DCKp90, DCKp135, DCKp180, DCKp225, DCKp270, and DCKp315 at the clock terminals, respectively. Flip-flops 550-557 receive processing clock PCK2 at data input terminal D. Then, the flip-flops 550-557 use the processing clock PCK2 received at the data input terminal D as the comparison information PSp and synchronize with the divided clock DCKp received at the clock terminal from the data output terminal Q to the phase information generator 558, respectively. Output.

  For example, the flip-flop 550 outputs the logical level (logical value) of the processing clock PCK2 when the frequency-divided clock DCKp0 rises to the phase information generator 558 as the comparison information PSp0. Similar to the flip-flop 440 described with reference to FIG. 3, the flip-flop 550 determines whether the phase of the processing clock PCK2 is delayed (or advanced) with respect to the phase of the divided clock DCKp0.

  Therefore, the comparison information PSp0 corresponds to information indicating a comparison result between the phase of the divided clock DCKp0 and the phase of the processing clock PCK2. For example, when the phase of the processing clock PCK2 is delayed from the divided clock DCKp45 and advanced from the divided clock DCKp90, the comparison information PSp45 and PSp90 have the logical values 0 and 1, respectively.

  The operation of the phase information generator 558 is the same as or similar to that of the selection information generator 450 shown in FIG. For example, the phase information generator 558 receives the comparison information PSp0, PSp45, PSp90, PSp135, PSp180, PSp225, PSp270, and PSp315 from the flip-flops 550-557, respectively. Phase information generator 558 generates phase information PINF based on comparison information PSp received from flip-flops 550-557. The phase information PINF generated by the phase information generator 558 is transferred to the phase adjustment unit 560.

  For example, the phase information PINF is divided into phase ranges of 0 ° (360 °), 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° with reference to the phase of the divided clock DCKp0. The phase of the processing clock PCK2 indicates in which phase range. That is, the phase information PINF corresponds to information indicating a comparison result (phase difference) between the phase of the processing clock PCK2 and the phase of the transmission clock SCK.

  In the example of FIG. 5, the phase range in which the phase of the processing clock PCK2 exists is selected from eight sections (eight sections shown in FIG. 6) divided by the eight-phase divided clock DCKp, so the number of bits of the phase information PINF is 3 bits or more. Hereinafter, description will be made assuming that the number of bits of the phase information PINF is 3 bits.

  For example, when the phase of the processing clock PCK2 is greater than (i−1) × 45 ° and equal to or less than i × 45 ° (i is an integer from 0 to 7), the phase information generator 558 sets the value of the phase information PINF to i. Set to. In this case, when the phase of the processing clock PCK2 is greater than 45 ° and less than or equal to 90 °, the value of the phase information PINF is set to 2.

  For example, when the phase of the processing clock PCK2 is greater than 45 ° and 90 ° or less, the comparison information PSp0, PSp45, PSp90, PSp135, PSp180, PSp225, PSp270, and PSp315 have logical values 0, 0, 1, 1, 1, 1, 0, 0. In this case, the phase information generator 558 detects the comparison information PSp90 as a location where the logical value switches from 0 to 1. Then, the phase information generator 558 sets a value (= 2) corresponding to the comparison information PSp90 in the phase information PINF.

  The phase adjustment unit 560 receives the lock information LINF and the n-phase (n is an integer of 1 or more) transmission clock SCK-n from the PLL circuit 530, and receives the phase information PINF from the phase information generator 558 of the phase comparison unit 540. . Then, the phase adjustment unit 560 supplies the processing clock PCK1 adjusted in phase based on the phase information PINF to the phase comparison unit 540 and the plurality of transmission units 400. For example, the phase adjustment unit 560 includes a fluctuation detection unit 562, a digital filter 565, a phase adjuster 569, and a frequency divider 570.

  The fluctuation detection unit 562 includes an initial value holding unit 563 and a subtraction unit 564. When the lock value LINF indicating that the frequency of the transmission clock SCK is stabilized is received from the PLL circuit 530, the initial value holding unit 563 uses the phase difference indicated by the phase information PINF received from the phase information generator 558 as the initial phase difference. Remember. The subtracting unit 564 subtracts the phase difference indicated by the phase information PINF received from the phase information generator 558 from the initial phase difference stored in the initial value holding unit 563, and outputs the subtraction result to the digital filter 565 as variation information VINF. . Hereinafter, the phases of the processing clock PCK, the transmission clock SCK, and the like when the initial phase difference is calculated are also referred to as an initial state.

  When the phase difference indicated by the phase information PINF is equal to the initial phase difference (when the phase of the processing clock PCK2 has not changed from the initial state), the value of the variation information VINF is 0. Further, when the phase difference indicated by the phase information PINF is smaller than the initial phase difference (when the phase of the processing clock PCK2 advances from the initial state), the value of the variation information VINF is positive. When the phase difference indicated by the phase information PINF is larger than the initial phase difference (when the phase of the processing clock PCK2 is delayed from the initial state), the value of the variation information VINF is negative.

  For example, when the initial phase of the processing clock PCK2 is greater than 45 ° and 90 ° or less, 2 is stored in the initial value holding unit 563 as the initial phase difference. When the phase of the processing clock PCK2 changes to a range greater than 0 ° and less than or equal to 45 ° (phase information PINF = 1), the subtracting unit 564 sets +1 (= 2-1) as the variation information VINF to the digital filter 565. Output. When the phase of the processing clock PCK2 changes to a range greater than 90 ° and less than or equal to 135 ° (phase information PINF = 3), the subtraction unit 564 sets −1 (= 2-3) as the variation information VINF to the digital filter 565. Output to.

  The digital filter 565 integrates the value of the fluctuation information VINF received from the fluctuation detection unit 562 and outputs the integration result to the phase adjuster 569 as the phase adjustment code PICODE. The cut-off frequency of the digital filter 565 is determined in advance based on, for example, the specifications of wander (corresponding wander) generated in the processing clock PCK. A digital filter 565 shown in FIG. 5 is a primary digital filter.

  For example, the digital filter 565 includes an amplifying unit 566, an adding unit 567, and a holding unit 568. The amplifying unit 566 amplifies the value of the variation information VINF received from the variation detecting unit 562 with the amplification factor G and outputs the amplified value to the adding unit 567.

  Adder 567 adds the information received from amplifier 566 (the value of fluctuation information VINF multiplied by G) to the value of phase adjustment code PICODE stored in holding unit 568. Thereby, the phase adjustment code PICODE is updated. The updated phase adjustment code PICODE is transferred to the holding unit 568 and the phase adjuster 569. Holding unit 568 holds the value of phase adjustment code PICODE received from addition unit 567. The number of bits of the phase adjustment code PICODE may be the same as the number of bits corresponding to the resolution of the phase adjuster 569 (3 bits in the example shown in FIG. 6), or the number of bits corresponding to the resolution of the phase adjuster 569 It may be larger.

  The phase adjuster 569 receives the n-phase transmission clock SCK-n from the PLL circuit 530 and the phase adjustment code PICODE from the digital filter 565. Then, the phase adjuster 569 adjusts the phase of the clock ICK having the same frequency (or substantially the same) as the frequency of the transmission clock SCK based on the phase adjustment code PICODE. For example, the phase adjuster 569 generates the clock ICK by weighting and combining the n-phase transmission clock SCK-n based on the phase adjustment code PICODE.

  When the number of bits of the phase adjustment code PICODE output from the digital filter 565 is larger than the number of bits corresponding to the resolution of the phase adjuster 569, the value of the upper bit of the phase adjustment code PICODE is used as the phase adjustment code. In the example shown in FIG. 6 (the number of bits corresponding to the resolution of the phase adjuster 569 = 3), the value of the upper 3 bits of the phase adjustment code PICODE is used as the phase adjustment code. For example, when the upper 3 bits of the phase adjustment code PICODE are 000, the phase of the clock ICK is adjusted to 0 °, and when the upper 3 bits of the phase adjustment code PICODE is 001, the phase of the clock ICK is adjusted to 45 °. .

  The phase adjuster 569 adjusts the phase of the clock ICK based on the initial phase adjustment code PICODE until the lock information LINF indicating that the frequency of the transmission clock SCK is stabilized is received from the PLL circuit 530.

  The frequency divider 570 divides the frequency of the clock ICK whose phase has been adjusted by the phase adjuster 569 to generate the processing clock PCK1. Thereby, the phase of the processing clock PCK1 is adjusted based on the phase adjustment code PICODE. For example, the frequency divider 570 supplies the processing clock PCK1 obtained by dividing the frequency of the clock ICK by 8 to the phase comparison unit 540 and the plurality of transmission units 400.

  Note that the configurations of the phase comparison unit 540 and the phase adjustment unit 560 are not limited to the example shown in FIG. For example, the phase adjustment unit 560 may include a clock selection unit that is the same as or similar to the clock selection unit 460 illustrated in FIG. 3 instead of the phase adjuster 569 and the frequency divider 570. In this case, the clock selection unit provided in the phase adjustment unit 560 receives the eight-phase divided clock DCKp from the phase generator 544, and uses one of the eight-phase divided clocks DCKp as the processing clock PCK1. Select based on the adjustment code PICODE.

  Further, the phase comparison unit 540 may be omitted from the clock generation unit 500. In this case, the phase adjustment unit 560 receives the selection information SINF as the phase adjustment code PICODE from one of the plurality of transmission units 400 (more specifically, the selection information generator 450 in the synthesizer 410), for example.

  That is, one of the second phase comparison units (a circuit including the frequency divider 420, the phase generator 430, the flip-flops 440-447, and the selection information generator 450) provided in each of the plurality of transmission units 400 is The phase comparison unit 540 of the clock generation unit 500 may also be used. In other words, the clock generation unit 500 may use one of the second phase comparison units provided in each of the plurality of transmission units 400 as the phase comparison unit 540. In this case, the circuit scale of the transmission circuit 300 can be reduced.

  FIG. 6 shows an example of the resolution of the phase adjuster 569 shown in FIG. In the example illustrated in FIG. 6, the phase adjuster 569 is, for example, any of the eight-phase clocks whose phases are shifted by 45 ° with reference to the phase of the transmission clock SCK supplied to the phase comparison unit 540 or the like. Is generated as a clock ICK. For example, when the upper 3 bits of the phase adjustment code PICODE are 000, 001, 010, 011, 100, 101, 110, 111, the phase of the clock ICK is 0 °, 45 °, 90 °, 135 °, 180 °, respectively. It is adjusted to 225 °, 270 °, and 315 °. Note that the resolution of the phase adjuster 569 is determined in advance based on, for example, the specifications of wander (corresponding wander) generated in the processing clock PCK.

  FIG. 7 shows an example of the operation of the clock generation unit 500 shown in FIG. The process of step S100 is executed after the PLL circuit 530 is activated or after the PLL circuit 530 is reset. Before the process of step S100 is executed, the phase of the clock ICK that is the source of the processing clock PCK1 is adjusted based on the initial phase adjustment code PICODE. That is, before the process of step S100 is executed, the phase comparison unit 540 and the plurality of transmission units 400 receive the processing clock PCK2 whose phase is adjusted based on the initial phase adjustment code PICODE.

  In step S100, the phase comparison unit 540 and the phase adjustment unit 560 determine whether the frequency of the output clock of the PLL circuit 530 is stable. For example, the phase comparison unit 540 and the phase adjustment unit 560 determine whether or not the transition to the locked state where the frequency of the transmission clock SCK is within a predetermined frequency range is made based on the lock information LINF received from the PLL circuit 530.

  When the frequency of the output clock of the PLL circuit 530 is not stable (when the frequency of the transmission clock SCK is not within a predetermined frequency range), the operation of the clock generation unit 500 returns to Step S100. When the frequency of the output clock of the PLL circuit 530 is stabilized (when the frequency of the transmission clock SCK is within a predetermined frequency range), the operation of the clock generation unit 500 proceeds to step S110.

  In step S110, the initial value holding unit 563 stores the initial value of the phase difference between the processing clock PCK2 and the transmission clock SCK. For example, the phase comparison unit 540 compares the phase of the processing clock PCK2 received via the processing circuit 200 with the phase of the transmission clock SCK, and phase information PINF indicating the phase difference between the processing clock PCK2 and the transmission clock SCK. Is output to the phase adjustment unit 560. Then, the phase adjustment unit 560 stores the phase difference indicated by the phase information PINF received from the phase comparison unit 540 in the initial value holding unit 563 as an initial phase difference.

  In step S120, the phase comparison unit 540 detects the phase difference between the processing clock PCK2 and the transmission clock SCK. For example, the phase comparison unit 540 compares the phase of the processing clock PCK2 received via the processing circuit 200 with the phase of the transmission clock SCK, and obtains phase information PINF indicating the phase difference between the processing clock PCK2 and the transmission clock SCK. Output to the phase adjustment unit 560.

  In step S130, the fluctuation detecting unit 562 calculates the phase change of the processing clock PCK2. For example, the fluctuation detection unit 562 subtracts the phase difference detected in step S120 (the phase difference indicated by the phase information PINF received from the phase comparison unit 540) from the initial phase difference stored in the initial value holding unit 563 in step S110. To do. Then, the fluctuation detection unit 562 outputs the subtraction result to the digital filter 565 as fluctuation information VINF.

  For example, when wander occurs in the processing clock PCK2 and the phase of the processing clock PCK2 is delayed from the initial state, the phase difference indicated by the phase information PINF is larger than the initial phase difference. In this case, the fluctuation information VINF output from the fluctuation detection unit 562 to the digital filter 565 is a negative value. When wander occurs in the processing clock PCK2 and the phase of the processing clock PCK2 advances from the initial state, the phase difference indicated by the phase information PINF is smaller than the initial phase difference. In this case, the fluctuation information VINF output from the fluctuation detection unit 562 to the digital filter 565 is a positive value.

  Note that when the phase of the processing clock PCK2 is the same as or substantially the same as the initial state (for example, a difference equal to or lower than the comparison accuracy of the phase comparison unit 540), the phase difference indicated by the phase information PINF is the same as the initial phase difference. In this case, the value of the fluctuation information VINF output from the fluctuation detecting unit 562 to the digital filter 565 is zero. That is, when no phase fluctuation is detected, the value of the fluctuation information VINF is zero.

  In step S140, the digital filter 565 updates the phase adjustment code PICODE based on the phase change of the processing clock PCK2 calculated in step S130. For example, the digital filter 565 integrates the value of the fluctuation information VINF received from the fluctuation detection unit 562 and updates the phase adjustment code PICODE.

  For example, when the phase of the processing clock PCK2 is delayed from the initial state, the digital filter 565 adds a negative value indicated by the fluctuation information VINF to the current phase adjustment code PICODE. For this reason, the value of the phase adjustment code PICODE is smaller than the current value. That is, when the phase of the processing clock PCK2 is delayed from the initial state, the digital filter 565 updates the phase adjustment code PICODE so that the phase of the processing clock PCK is advanced from the current phase.

  For example, when the phase of the processing clock PCK2 advances from the initial state, the digital filter 565 adds a positive value indicated by the fluctuation information VINF to the current phase adjustment code PICODE. For this reason, the value of the phase adjustment code PICODE is larger than the current value. That is, when the phase of the processing clock PCK2 advances from the initial state, the digital filter 565 updates the phase adjustment code PICODE so that the phase of the processing clock PCK is delayed from the current phase.

  When the value of the fluctuation information VINF is 0 (when no phase fluctuation is detected in step S130), the phase adjustment code PICODE is maintained at the current phase adjustment code PICODE.

  In step S150, the phase adjustment unit 560 adjusts the phase of the processing clock PCK1 based on the phase adjustment code PICODE updated in step S140. For example, when the phase of the processing clock PCK2 is delayed from the initial state, the phase adjuster 569 advances the phase of the clock ICK from the current phase in order to receive the phase adjustment code PICODE updated to a value smaller than the current value. For this reason, the phase of the processing clock PCK1 obtained by dividing the frequency of the clock ICK advances from the current phase.

  For example, when the phase of the processing clock PCK2 advances from the initial state, the phase adjuster 569 receives the phase adjustment code PICODE updated to a value larger than the current value, so that the phase of the clock ICK is changed from the current phase. Delay. For this reason, the phase of the processing clock PCK1 obtained by dividing the frequency of the clock ICK is delayed from the current phase.

  In this way, the clock generation unit 500 adjusts the phase of the processing clock PCK1 so as to restore the phase shift of the processing clock PCK2 due to the wander. After the process of step S150 is executed, the operation of the clock generation unit 500 returns to step S120. The clock generation unit 500 suppresses the generation of wander in the processing clock PCK2 received by the phase comparison unit 540 and the plurality of transmission units 400 by repeating the processing of steps S120 to S150. Note that the operation of the clock generation unit 500 is not limited to the example shown in FIG.

  As described above, also in the embodiment shown in FIG. 2 to FIG. 7, the same effect as that of the embodiment shown in FIG. For example, the influence of wander of the clock (processing clock PCK2) in the transmission circuit 300 can be reduced without increasing the delay time of the transmission circuit 300. Since the delay time of the transmission circuit 300 can be reduced, the latency of the integrated circuit 100 can be reduced. That is, the influence of the wander of the processing clock PCK2 can be reduced without increasing the latency of the integrated circuit 100.

  Further, even when the wander generated in the processing clock PCK increases as the number of the transmitting units 400 increases, each transmitting unit 400 receives the processing clock PCK2 in which the generation of wander is suppressed. For this reason, even when the number of transmission units 400 increases, the influence of the wander of the processing clock PCK2 can be reduced without increasing the delay time of the transmission circuit 300.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... Integrated circuit; 20 ... Processing circuit; 22 ... Clock wiring; 30 ... Transmission circuit; 40 ... Transmission part; 50 ... Clock generation part; 52 ... Clock output terminal; Lane; 100 integrated circuit; 200 processing circuit; 202 clock wiring; 210-245 clock driver; 300 transmission circuit; 400 transmission unit; 410 synthesizer; 420 frequency divider; 440-447 Flip-flop; 450 Selection information generator; 460 Clock selector; 470 Multiplexer; 480 Output buffer; 500 Clock generator; 520 Clock output terminal; Phase comparison unit; 542 · frequency divider; 544 · phase generator; 550 to 557 · flip-flop · 558 · phase information 560... Phase adjustment unit; 562... Fluctuation detection unit; 563... Initial value holding unit; 564. 569; 570 ... frequency divider; 600 ... lane

Claims (6)

A processing circuit for generating data;
And a transmission circuit for transmitting the data generated by the processing circuit,
The transmission circuit includes:
A clock generator for supplying a first processing clock and a transmission clock;
The second processing clock and the transmission clock having a phase shifted from the phase of the first processing clock are received, the data synchronized with the second processing clock is received from the processing circuit in synchronization with the reception clock, and received. A plurality of transmitters for transmitting the received data in synchronization with the transmission clock,
The clock generator is
A phase comparator for comparing the phase of the second processing clock and the phase of the transmission clock;
Based on the comparison result in the phase comparator, it has a phase adjustment unit for adjusting the first process clock phase,
The first processing clock after passing through the processing circuit from the clock generation unit is supplied to the phase comparison unit and the plurality of transmission units as the second processing clock,
Each of the plurality of transmission units includes a second phase comparison unit that compares the phase of the second processing clock and the phase of the transmission clock, and is based on the comparison result in the second phase comparison unit. To generate the reception clock
An integrated circuit characterized by that. The integrated circuit of claim 1, wherein
The clock generation unit has a clock output terminal that outputs the first processing clock;
The processing circuit is connected to the phase comparison unit and the plurality of transmission units, and has a branch wiring arranged with the load of the wiring from the clock output terminal to the phase comparison unit and the plurality of transmission units aligned. ,
The branch wiring branches the first processing clock output from the clock output terminal into a plurality of branches, and transmits one of the branched first processing clocks as the second processing clock to the phase comparison unit. An integrated circuit characterized by that. The integrated circuit of claim 2, wherein
The branch wiring is
A plurality of clock drivers for shaping the waveform of the first processing clock;
An integrated circuit, comprising: a dummy clock driver for aligning a skew of the second processing clock received by the phase comparison unit with a skew of the second processing clock received by the plurality of transmission units. The integrated circuit according to any one of claims 1 to 3 ,
The data synchronized with the second processing clock is parallel data including a plurality of bits, and the data transmitted in synchronization with the transmission clock is serial data,
The second phase comparison unit divides the frequency of the transmission clock to generate a plurality of divided clocks having different phases, and uses the plurality of divided clocks to determine the phase of the second processing clock. Compare the phase of the transmission clock,
Each of the plurality of transmitters is
Before SL based on the comparison result of the second phase comparator, a clock selector for selecting the received clock from among the plurality of divided clock,
Parallel data synchronized with the second processing clock is received from the processing circuit in synchronization with the reception clock, the parallel data received from the processing circuit is converted into serial data, and the converted serial data is synchronized with the transmission clock. And a multiplexer unit for transmitting
One of the second phase comparison units provided in each of the plurality of transmission units is also used as the phase comparison unit of the clock generation unit. In the transmission circuit that transmits the data generated by the processing circuit,
A clock generator for supplying a first processing clock and a transmission clock;
The second processing clock and the transmission clock having a phase shifted from the phase of the first processing clock are received, the data synchronized with the second processing clock is received from the processing circuit in synchronization with the reception clock, and received. A plurality of transmitters for transmitting the received data in synchronization with the transmission clock,
The clock generator is
A phase comparator for comparing the phase of the second processing clock and the phase of the transmission clock;
Based on the comparison result in the phase comparator, it has a phase adjustment unit for adjusting the first process clock phase,
The first processing clock after passing through the processing circuit from the clock generation unit is supplied to the phase comparison unit and the plurality of transmission units as the second processing clock,
Each of the plurality of transmission units includes a second phase comparison unit that compares the phase of the second processing clock and the phase of the transmission clock, and is based on the comparison result in the second phase comparison unit. To generate the reception clock
A transmission circuit characterized by that. The transmission circuit according to claim 5 , wherein
The data synchronized with the second processing clock is parallel data including a plurality of bits, and the data transmitted in synchronization with the transmission clock is serial data,
The second phase comparison unit divides the frequency of the transmission clock to generate a plurality of divided clocks, and uses the plurality of divided clocks to determine the phase of the second processing clock and the transmission clock. Compare with the phase of
Each of the plurality of transmitters is
Before SL based on the comparison result of the second phase comparator, a clock selector for selecting the received clock from among the plurality of divided clock,
Parallel data synchronized with the second processing clock is received from the processing circuit in synchronization with the reception clock, the parallel data received from the processing circuit is converted into serial data, and the converted serial data is synchronized with the transmission clock. And a multiplexer unit for transmitting
One of the second phase comparison units provided in each of the plurality of transmission units is also used as the phase comparison unit of the clock generation unit.

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