JPH04142832A - Timing signal distributer - Google Patents

Abstract

PURPOSE:To make the propagation delay between taps to be only the propagation delay of a traveling wave by applying phase modulation to a 2nd timing signal based on a 1st timing signal and demodulating the 2nd timing signal from a signal distributed and modulated by a signal processing section so as to make the relation of phase constant. CONSTITUTION:A timing signal generating section 11 is provided with a phase modulation circuit 113 and a frame signal obtained by a frequency divider 112 is phase-modulated by a clock signal CK1 and the clock signal CK1 and a modulation frame signal CK2' are sent to transmission lines A, B on a mother board 12 and fed to signal processing sections 131-13N via N sets of taps. Then phase demodulation circuits 1311-13N1 of the signal processing sections 131-13N demodulate the frame signal CK2' modulated by the timing signal generating section 11 by using the clock signal CK1. Thus, the relation of phase between various timing signals is independent of the location of tap and the time difference inputted to each board depends only on the propagation delay of a traveling wave traveling on the transmission lines A, B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a timing signal distribution device that distributes timing signals to a plurality of signal processing units.

(Prior art) When a clock signal and a timing signal such as a frequency-divided clock signal obtained by dividing the clock signal are distributed to signal processing circuits formed on a plurality of printed circuit boards via a transmission line on the Masabo I. Conventionally, distribution is performed on a printed circuit board on which a timing signal generation circuit is formed, and each distributed timing signal is sent to a plurality of transmission lines formed on a motherboard, so that it is transmitted to a corresponding signal processing circuit. We are trying to distribute the supply.

With this configuration, if the number of distributions is small, the motherboard 1.
Since the number of transmission lines is small, with only one transmission end and one reception end, even if the clock signal frequency reaches several hundred MHz, it can be easily matched to the characteristic impedance of the wiring on the motherboard. I can do it. However, as the number of distribution increases, the number of transmission lines on the motherboard will inevitably increase.
As the frequency of the clock signal increases, the effects between lines cannot be ignored.

For this reason, conventionally, a plurality of timing signals having a specific phase relationship with each other, such as a clock signal generated by a timing signal generator and a frequency-divided clock signal, are passed through the motherboard one by one, and each signal processing A method is used in which the signal is lowered by tapping. This method is often used in frame synchronization devices such as synchronous multiplexers and cross-connect devices.

FIG. 3 shows the configuration of the above frame synchronization device.
11 is a printed circuit board on which a timing signal generation circuit is formed (hereinafter referred to as a timing signal generation section), 12 is a motherboard on which a transmission line is formed, and 131 to 13N are printed circuit boards on which a signal processing circuit is formed (hereinafter referred to as a timing signal generation section). 14 is a printed circuit board (hereinafter referred to as a signal processing section) on which a termination circuit for impedance matching and termination of the transmission line on the motherboard 12 is formed.
(referred to as the terminal end).

The N signal processing units 131 to 13N use a clock signal (hereinafter referred to as a reference clock signal) CK as a reference for operation.
+ and a clock signal for frame generation of a pig signal obtained by dividing the clock signal (hereinafter referred to as a frame signal)
Requires CR2. Each signal processing section 13□ to 13N is
Input basic clock signal CK and frame signal CK
2. Output the processed data signal according to 2.

Timing signal generator] 1 is the basic clock signal CK
A signal source that generates 1] 1□ and a frequency divider that divides the output of this signal source] 11 to generate a frame signal CK2] 12
This timing signal generator 11 often includes a circuit synchronized with an external highly stable clock source.The frequency of the clock signal CK is several hundred MHz, and the frame signal CK2 is, for example, 31 cHz. has a repetition frequency of

The motherboard] 2 takes in the clock signals CK, . ~13N, and further sent to the terminal section 14. Furthermore, each signal processing section 1'3. ~13N
Take in the pig signal output from the transmission line 01~
It is sent to the termination section 14 via CN.

The terminal part 14 receives the clock signal CK from the motherboard 12.
,, takes in the frame signal cK2 and sends it to the motherboard 1.
It is impeded and terminated with the two transmission lines A and B. Further, the output data signals of the respective signal processing units 131 to 13N from the motherboards C] to CN are taken in and further data signal processing is performed. Examples of such data signal processing include multiplexing processing in the case of a multiplexing device and switching in the case of a cross-connect device.

By the way, the clock signal CK on the motherboard 12,
and frame signal cK2 have a specific phase relationship, and the clock signal C is input to each signal processing unit 13, to 13N.
K, ... CK, N, frame signal CK 21- CK
If 2N have the same phase relationship, for example, the ]th signal processing unit 13 □ and the signal processing unit 13 of
The time difference between the timing input to N is the motherboard 12.
The above propagation delay is the only one. Similarly, the same propagation delay occurs due to the time difference between the data signal outputs of the signal processing units 131 and 13N.

Therefore, each signal processing section input to the termination section 14]3
, ~13N data signals have the same frame phase.

However, the clock signal CK on the motherboard 12
, and the transmission lines A and B of the frame signal CK 2 have characteristic impedances of taps to the signal processing units 1'3 and 13N. In all four cases, a capacitor is added to the transmission line. In this case, the termination part 14 may not be properly matched, and the clock signal CK on the massaboard board 2 may not be properly matched.
,, the standing wave of the frame signal CK2 gets on it. Due to the influence of this standing wave, for example, the phase difference between the clock signal CK + + to the signal processing section] 31 and the clock signal CKIN to the signal processing section 13N is not only due to the propagation delay of the traveling wave.

Since this influence varies depending on the difference in the frequency of the standing waves, the clock signals Ck + + to CK and the frame signal CK21 manually input to each (.13. to 1.3N)
The phase relationship between ~CI<2N will differ depending on the position on the motherboard 12. Considering on the frequency axis,
The above phenomenon occurs because the group delay on the motherboard 12 differs depending on the frequency.

In order to avoid this, is there a way to increase the impedance by inserting a resistor into the tap line?Increasing this resistance will narrow the frequency band after the tap, so
At present, it is not possible to insert a very large resistance, and as a result, little or no effect can be obtained.

(Problems to be Solved by the Invention) As described above, in the conventional timing signal distribution device,
When the phase relationship between multiple timing signals that should have a specific phase relationship, such as a clock signal and its frequency divided clock signal, is drawn from the motherboard to each signal processing unit using taps, it is determined by the capacitance of the transmission line wiring and the taps. The problem was that it differed depending on the location.

This invention was made in order to solve the above problem, and the phase relationship between various timing signals depends on the tap location. 1. To provide a timing signal distribution device whose timing is determined only by wave propagation delay.
Let's say it's 1.

[Configuration of the Invention (Means for Solving the Problem) In order to achieve the above object, a timing signal distribution device according to the present invention includes a timing signal distribution device that generates first and second timing signals having a specific phase relationship with each other. A signal generator, a motherboard that sends a timing signal output from the timing signal generator to a transmission line and distributes it to multiple systems using multiple taps provided on the transmission line, and a motherboard that distributes the timing signal from the taps of the motherboard, respectively. The X
phase shifter 1g21 means for phase modulating the second timing signal based on the timing signal of S1 and supplying the modulated signal to the motherboard; The device is configured to include phase demodulation means that receives the modulated signal from a tap on the motherboard and demodulates the second timing signal.

(Function) In the timing signal distribution device having the above configuration, the timing signal generating unit side modulates the phase of the second timing signal based on the first timing signal, and the signal processing unit side modulates the phase of the second timing signal from the taps on the motherboard. By demodulating the second timing signal from the modulated signal, the impedance of the tap on the motherboard is increased, and the phase relationship of the plurality of timing signals drawn into each signal processing section can all be made constant. The propagation delay between the two is set to be only that of the traveling wave.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. However, in FIG. 1, the same parts as in FIG. 3 are denoted by the same reference numerals, and the different parts will be mainly explained here.

Although FIG. 1 does not show its configuration, a phase modulation circuit] 13 is further added to the timing signal generator 1], and a frame signal CK2 obtained by the frequency divider 1]2 is used as a clock signal C.
K1 is phase modulated and a modulated frame signal CI2' is output. These clock signals CK
, and modulated frame signal CI (2' is the motherboard) 2 are sent to the transmission line AB, and are supplied to the signal processing units 131 to 1.3N via N taps, and are also supplied to the termination unit 13. is terminated.

On the other hand, the signal processing units 131 to 13N include a phase demodulation circuit]3
□, ~13N1 is added, timing signal generator] 1
The frame signal CK2 modulated by the clock signal CK
1 demodulation.

As shown in FIG. 2, the phase modulation circuit 113 can be realized by exclusive ORing the clock signal CK and the frame signal CK2.

Conversely, the phase demodulation circuits 1311 to 13N1
] This can be realized by calculating the exclusive OR of the clock signal CK2' and the clock signal CK. Here, the spectral distributions of the clock signal CK and the modulated frame signal CK2 are almost the same, and the modulated frame signal CK2' only exhibits a wider spread due to the phase modulation property.

As described above, when the impedance of the taps of the motherboard 12 is increased, the passbands of the tap input sections of the signal processing sections 131 to 13N are limited.

However, even if the tap section has frequency characteristics, the clock signal CK and the modulated frame signal CK2' have almost the same frequency spectrum and are close to a single spectrum, so no distortion occurs and a linear loss occurs.

Therefore, the timing signal distribution device with the above configuration can increase the impedance of the tap section, and the clock signal CK drawn into each signal processing section 131 to 13N,
The phase relationship between the modulated frame signal CK2' and the modulated frame signal CK2' can all be kept constant. Furthermore, good matching at the terminal end 14 can be maintained, and the propagation delay between the taps can be reduced to only the propagation delay of the traveling wave.

[Effects of the Invention] As described above, according to the present invention, the phase relationship between various timing signals does not depend on the location of the tap, and the time difference manually applied to each timing signal board or the traveling wave traveling on the transmission line It is possible to provide a timing signal distribution device in which the timing signal is determined only by the propagation delay of the signal.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a timing signal distribution device according to the present invention, FIG. 2 is a timing waveform diagram for explaining the operation of a phase modulation circuit and a phase demodulation circuit of the same embodiment, and FIG. The figure is a block diagram showing an example of a conventional timing signal distribution device. 11... Timing signal generation unit, 11□... Clock signal source, ] 12... Frequency divider, 1] 3 - Phase modulation circuit, 12... Motherboard, 131 to 13N - Signal processing unit, 1311-13N1 phase recovery: A circuit, 14 termination section,
CK, Clock signal, CR2 frame 1'3 frame signal, A... Clock signal transmission line, B... Frame signal transmission line, 01 to CN... Data transmission line.

Claims (3)

[Claims] (1) A timing signal generation section that generates first and second timing signals having a specific phase relationship with each other, and a timing signal outputted from this timing signal generation section that is provided on the transmission line. A circuit device comprising a motherboard that distributes signals to a plurality of systems using a plurality of taps, and a plurality of signal processing sections that input timing signals distributed from the taps of the motherboard and perform signal processing using these timing signals. is,
a phase modulation means provided in the timing signal generation section, phase modulating the second timing signal based on the first timing signal and supplying the modulated signal to the motherboard; and the plurality of signal processing units. a timing signal distribution device, the timing signal distribution device comprising: a phase demodulation means which is individually provided in each section, is supplied with the modulated signal from a tap of the motherboard, and demodulates the second timing signal. (2) The first timing signal is a basic clock signal of the signal processing section, and the second timing signal is a frame signal obtained by frequency-dividing this basic clock signal. The timing signal distribution device according to claim 1. (3) The phase modulation means is configured to take an exclusive OR of the basic clock signal and the frame signal, and the phase demodulation means is configured to take a modulated frame phase-modulated by the basic clock signal and the phase modulation means. 3. The timing signal distribution device according to claim 2, wherein the timing signal distribution device is configured to take an exclusive OR with the signal.