KR100242706B1 - Apparatus for receiving trunk clock in an electronic switching system - Google Patents

Abstract

The present invention relates to a relay line clock receiving apparatus which receives a clock of an E1 / T1 relay line at an all-electronic exchange and automatically recognizes a reference clock and converts the reference clock into a reference clock of the exchange, regardless of the reference clock of the relay line. In the technology, the clock of 2.048MHz is received from the E1 relay line to make a reference clock of 4 KHz, which is the reference clock signal used in the exchange, and the line and circuit input from the T1 relay line are separated from the E1 relay line. Since the input 1.544MHz clock signal is converted into a 4KHz signal, which is the reference clock signal of the exchanger, there is a drawback in that the device must be connected differently according to the input signal. However, in the present invention, the 2.048KHz input signal is input from the E1 relay line. In addition to receiving and processing clock signals, a 1.544KHz clock signal input from the T1 trunk By receiving and receiving two signals by checking the error and the order of the input signals, and processing the clock as a reference clock, the above-mentioned defect can be improved by generating a reference clock used for the exchange regardless of the clock of the input relay line. It is.

Description

Relay line clock receivers in electronic switchboards

The present invention relates to a relay line clock receiving device in an all-electronic exchange, and more particularly, to receive a clock of an E1 / T1 relay line in an all-electronic exchange, and automatically recognizes a reference clock regardless of the reference clock of the inputted relay line, to the reference clock of the exchange. It relates to a trunk line clock accommodating device that is used by converting.

Referring to FIG. 1, a block diagram of a relay line clock accommodating device in an all-electronic switch suitable for accommodating a relay line clock in the prior art is described. A first relay line among inputs received by clock selection through a multiplexer 104 is described. When 101 or the second relay line 102 is selected, the multiplexer 104 selects one of the received first relay line 101 signal or the second relay line 102 signal to convert the two-wire signal into a single-wire signal. Switch to

The clock divider 108 receives the clock signal of E1 / T1 input through the multiplexer 104 from one circuit of the T1 relay line or E1 through the first relay line 101 or the second relay line 102. The received clock signal is divided to produce a desired reference clock.

The analog phase locked loop 110 is an element that generates an arbitrary frequency by an external signal. The analog phase locked loop 110 includes a phase comparator, a low pass filter, an error amplifier, and a voltage controlled oscillator to divide a clock divider to reach a desired reference clock. A signal of 4MH is received from the 108 and looped back to produce a frequency of 4KHz, the desired reference clock.

Oscillator 112 oscillates the reference frequency to generate the desired clock frequency at the exchange and uses the generated clock frequency as needed.

However, in the related art, a clock of 2.048 MHz is received at the E1 relay line to make a 4 KHz reference clock, which is a reference clock signal used in the exchange, and the lines and circuits input from the T1 relay line are different from the E1 relay line. Aside from this, the 1.544MHz clock signal input from the T1 relay line is converted into a 4KHz signal, which is the reference clock signal of the exchanger, so that the devices must be connected differently according to the input signal.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and T1 / T1 to convert the relay line reference clock signals of T1 and E1 input through the relay line in the all-electronic exchange into a reference clock signal used in the exchange. An object of the present invention is to provide a clock accommodating device in a relay line of an all-electronic switch that can accommodate all reference clock signals of an E1 relay line.

In order to achieve the above object, the present invention provides a first divider and a second divider for receiving a clock signal of E1 / T1 and dividing the received clock signal to produce a desired reference clock, and a first relay line and a first divider. A clock selection circuit for checking a clock signal received from the two relay lines to select the first relay line or the second relay line, and a multiplexer for converting the two-wire signals received at the first and second dividers into one-wire signals; Provided is a relay line clock accommodating device in an all-electronic exchange.

1 is a block diagram of a relay line clock accommodating device in an all-electronic switch suitable for accommodating the relay line clock according to the prior art;

Figure 2 is a block diagram of a relay line clock receiving device in an all-electronic switch suitable for receiving the relay line clock according to the present invention.

<Description of the code | symbol about the principal part of drawing>

205: first divider 206: second divider

210: multiplexer 212: clock selection circuit

214: analog phase locked loop 216: oscillator

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

The configuration of the present invention includes a first divider 205 and a second divider 206 for receiving a clock signal of E1 / T1 and dividing the received clock signal to produce a desired reference clock, and each of the relay lines ( Multiplexer which checks the input received from 201, 202, selects the first relay line 201 or the second relay line 202 using the clock selection circuit 212, and converts the received two-wire signal into a one-wire signal. 210, an analog phase locked loop 214, which is a device for generating a frequency of 4 KHz by an external signal, and an oscillator 216 for oscillating the reference frequency to generate a desired clock frequency.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

First, referring to FIG. 2, a block diagram of a relay line clock accommodating device in an all-electronic switch is suitable for accommodating a relay line clock. Referring to FIG. 2, the first divider 205 and the second divider 206 have input T1 relay lines. Regardless of whether it is input from E1 or E1 relay line, it receives the input clock signal of E1 / T1 and divides the received clock signal to produce the desired reference clock and divides it into 4MHz signal.

First trunk clock 2nd trunk clock First switch 2nd switch E1 E1 ON ON E1 T1 ON OFF T1 E1 OFF ON T1 T1 OFF OFF

As shown in Table 1 above, when the clocks input from the first relay line 201 and the second relay line 202 are all E1 clocks, both the first switch 203 and the second switch 204 are turned off to prevent grounding. ″ 1 ″ data is entered.

For example, both of the relay lines connected to the first switch 203 and the second switch 204 are turned off, and the clock of the relay line inputted by receiving data of 11111100 is E1 in both the first and second relay lines 201 and 202. Recognize that it is a clock of the form.

When the E1 signal is input at the first relay line 201 and the T1 signal is input at the second relay line 202, the first relay line 201 connected to the first switch 203 is turned off, and the second switch 204 is input. It is turned on in the second relay line 202 connected to).

Since the relay line connected to the OFF position is not grounded, data of ″ 0 ″ is input where the data of ″ 1 ″ is grounded.

For example, the first relay line 201 connected to the first switch 203 is turned off to receive a signal of 11111100, and the second relay line 202 connected to the second switch 204 is turned on to receive a signal of 00000000. .

When the T1 signal is input at the first relay line 201 and the E1 signal is input at the second relay line 202, the first relay line 201 connected to the first switch 203 is turned on, and the second switch 204 is input. Is connected to the second relay line 202 is turned OFF.

For example, the first relay line 201 connected to the first switch 203 is turned on to receive a signal of 00000000, and the second switch 202 connected to () is turned off to receive a signal of 11111100. .

When the clocks input from the first relay line 201 and the second relay line 202 are both T1 clocks, data of ″ 0 ″ grounded by turning on both the first switch 203 and the second switch 204 is input. do.

For example, both of the relay lines connected to the first switch 203 and the second switch 204 are turned on to receive 00000000 data, and the clock of the relay line inputted therein is T1 for both the first and second relay lines 201 and 202. Recognize that it is a clock of the form.

Each of the first and second dividers 205 and 206 is an apparatus for giving an output signal having a frequency that is a divisor of the input signal frequency, and the input / output frequency is not necessarily an integer ratio.

When the first relay line 201 or the second relay line 202 is selected among the input clocks received by the clock selection circuit 212 through the multiplexer 210, the multiplexer 210 receives the first relay line signal 207. Alternatively, one of the second relay line signals 208 is selected.

That is, the clock selection circuit 212 checks whether the signal is normally input from the first relay line 201 or the second relay line 202, and selects a signal input first, and then the first relay line 201 or the second relay line ( If an error occurs in the clock received at one of the relay lines, a signal of the relay line in which the error does not occur is selected and received.

If the clock signal input from the first relay line 201 and the second relay line 202 is abnormal, the multiplexer 210 processes the signal as an error without receiving the signal.

The multiplexer 210 converts the two-wire signal into a single-wire signal in the manner described above.

The analog phase locked loop 214 is an element that generates an arbitrary frequency by a signal from the outside, and is composed of a phase comparator, a low pass filter, an error amplifier, and a voltage controlled oscillator, and a signal 211 of 4KHz from the multiplexer 210. ) Is looped back to reach the desired reference clock to produce a reference frequency 213 of 4KHz, which is the desired reference clock.

Oscillator 216 vibrates 4KHz reference frequency 213 from analog phase locked loop 214 to generate the desired clock frequency at the exchange.

As described above, the present invention not only receives and processes a 2.048 KHz clock signal input from the E1 relay line, but also receives a 1.544 KHz clock signal input from the T1 relay line, thereby providing an error and a sequence of signals inputted to the two signals. By checking and receiving and processing the clock as a reference clock, the clock select signal uses the existing signal, and if configured on an existing printed board, it can be easily added to the existing PCB and used in the exchange regardless of the incoming relay clock. There is an effect of generating a reference clock.

The principles of the invention have been described above in connection with specific devices, which are described by way of example only, and are not limited to the spirit of the invention as described in the appended claims.

Claims (6)

A first divider 205 and a second divider 206 for receiving a clock signal of the input E1 / T1 and dividing the received clock signal to produce a desired reference clock; A clock selection circuit 212 for checking the clock signals received from the first relay line 201 and the second relay line 202 to select the first relay line 201 or the second relay line 202; The apparatus for accepting a relay line clock in an all-electronic switch comprising a multiplexer (210) for converting two-wire signals received by the first divider (205) and the second divider (206) into a single-wire signal. The method of claim 1, When the clocks input from the first relay line 201 and the second relay line 202 are both E1 clocks, Relay line clock accommodating device in an electronic switch, characterized in that the first switch (203) and the second switch (204) is turned off. The method of claim 1, When the E1 signal is input at the first relay line 201 and the T1 signal is input at the second relay line 202, The first relay line 201 connected to the first switch 203 is turned off, and the second relay line 202 connected to the second switch 204 is turned on. Device. The method of claim 1, When the T1 signal is input at the first relay line 201 and the E1 signal is input at the second relay line 202, The first relay line 201 connected to the first switch 203 is turned on, and the second relay line 202 connected to the second switch 204 is turned off. Device. The method of claim 1, When the clocks input from the first relay line 201 and the second relay line 202 are both T1 clocks Relay line clock accommodating device in the electronic switchboard, characterized in that both the first switch (203) and the second switch (204) is turned on. The method of claim 1, The clock select circuit 212, That is, checking the clock selection circuit (212) whether the signal is normally input from the first relay line (201) or the second relay line (202) and selecting the first input signal; Selecting and inputting a signal from a relay line in which no error occurs when an error occurs in a clock received from one of the first relay line 201 or the second relay line 202; If both clock signals inputted from the first relay line (201) and the second relay line (202) are abnormal, the relay line clock accommodating device of the all-electronic switchboard is characterized in that the step of processing as an error without receiving the signal.

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