GB2128824A

GB2128824A - Clock pulse generation circuit

Info

Publication number: GB2128824A
Application number: GB08228607A
Authority: GB
Inventors: Gary Alfred Sarson
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1982-10-06
Filing date: 1982-10-06
Publication date: 1984-05-02

Abstract

A clock pulse generation circuit e.g. for use in a digital telephone exchange is capable of operating as a free-running system when connected to the network over analogue trunks, or in synchronism with the network clock when connected to the network via digital trunks. The circuit is based on a phase-locked loop including a crystal (X) controlled voltage-controlled oscillator (VCO) whose output forms one input of a phase comparator (PC). The latter has a second input (RC) on which a remote clock is received when the exchange is connected via digital trunks. The phase comparator, in the absence of a clock pulse train on the second input (RC), emits a condition which causes the oscillator (VCO) to run at its mid-frequency. However, if a remote clock is received on the phase comparator's second input (RC), the comparator (PC) produces a condition dependent on the relation between the remote clock and the oscillator output. This forces the oscillator into synchronism with the remote clock. The change between the operating condition occurs automatically. <IMAGE>

Description

SPECIFICATION Clock pulse generation circuit This invention relates to a clock pulse circuit for use in a digital system, such as an automatic telephone exchange.

Where a digital system has to be used with an analogue (i.e. non-digital system) its clock pulse generation circuit is free-running, but when used with another digital system it is desirable for the two to be in synchronism. This invention has as its object the provision of a clock pulse generation circuit usable in either of these circumstances.

According to the invention, there is provided an electrical clock pulse generation circuit for use in a digital system, which operates as a free-running circuit when not connected to another digital system but which when connected to another digital system runs in synchronism with the clock of that other digital system, which circuit includes a phase-locked loop including an oscillator and a phase comparator, wherein the phase comparator has a first input to which the output of the oscillator is connected and a second input to which the clock of the other digital system may be connected, wherein when no clock pulse train is connected to the phase comparator the latter applies to the oscillator a control condition which causes that oscillator to run at its nominal frequency, and wherein when a clock pulse train is connected to the second input of the phase comparatorthe latter produces a control condition dependent on the relation between that clock pulse train and the oscillator output, which output condition forces the oscillator into a condition in which its output is in synchronism with the clock pulse train applied to said second input.

An embodiment of the invention will now be described with reference to the accompanying highly schematic block diagram.

The clock pulse generation circuit shown was developed for use in a digital telephone exchange such as that described and claimed in our Appiication No (G.A. Sarson et al 5-4-1).

The above-mentioned exchange is a "small" business-type telephone exchange, in which calls are set up in TDM manner using PCM to convey speech, and also data if the exchange serves any data terminals.

The exchange has subscriber line ports each serving two lines and a smaller number of trunk line ports each serving a trunk to a local exchange. Each port has a local processor with analogue-digital and digital to analogue conversion circuitry. The exchange also has a central processor with its associated memories.

The ports and the central processor are intercconnected by an intelligence bus and a signalling bus. The central processor and the port processors co-operate in call setting with all communications between the processors over the signalling bus.

During operation the central processor polls the ports via the signalling bus for ports needing the services of the central processor and also to pass call control information to those ports.

To set up a call between two lines, or a line and a trunk, two time slots in the TDM cycle are allocated to the call by the central processor, one for each direction of transmission. The intelligence bus is thus used only to convey intelligence, i.e. speech and/or data and tones. This simplifes the design of the speech circuitry of the telephone.

Such an exchange may have to be connected to an analogue local exchange, in which case its clock pulse generation circuit can be free-running. However, it may also have to be connected to a digital exchange, in which case its clock pulse generation circuit should produce clock pulses which are in synchronism with those from the local exchange. To avoid the need for providing two types of clock pulse generation circuit, the arrangement described herein is free-running when not connected to a digital exchange, but when so connected it automatically sets itself to a condition in which it is in synchronism with the local exchange clock.

The clock system shown in the drawing generates two clock pulse trains, referred to as PCMCLK and FRMSYNC respectively, which control all data on the intelligence bus or PCM bus of the telephone exchange referred to above. PCMCLK has a frequency of 2.048 MHz +/-50 ppm, and the FRMSYNC undergoes a positive transition on every 256 th PCMCLK positive edge. FRMSYNC produces each of its positive transitions at the commencement of a TDM-PCM frame of the exchange.

When the telephone exchange is connected to the National network via analogue trunks the clock system itself controls all timing. However, when connected via digital trunks the internal clock must be synchronous with the clock used on the trunks.

The clock system described herein automatically performs this synchronisation when a digital trunk is connected, by using a phase locked loop circuit. This has the same effect as physically switching off the internal clock and connecting to the external one.

The clock circuit is based on a Ferranti UAA, reference with a 8.192 MHz crystal. The UAA contains a Voltage Controlled Oscillator VCO, which forms part of a phase locked loop circuit. A phase comparator PC, which is the error detector in the loop, generates a voltage which is dependent on the phase difference between the VCO output and the remote clock input. This input is received over an input designated RC. The derived voltage is applied to the VCO via a phase lag filter PLF which smoothes out the high frequency components of the comparator output.

When no remote clock is present, the control inputs of the VCO are both set to 2.5v by the comparator PC, which causes the oscillator to free run at its centre frequency. When the remote clock is present on the input RC, the VCO frequency is pulled (within the limits of +/-50 ppm) to the same frequency as the remote clock.

The output of the VCO is divided by 4 to provide PCMCLK, and this output is itself connected to a counter stage which divides by 256 to generate FRMSYNC.

The remote clock is automatically connected to the clock circuit whenever a digital line card is fitted to the exchange, or whenever the exchange is con nected to the telephone network via a digital trunk or trunks.

Claims

1. An electrical clock pulse generation circuit for use in a digital system, which operates as a freerunning circuit when not connected to another digital system but which when connected to another digital system runs in synchronism with the clock of that other digital system, which circuit includes a phase-locked loop including an oscillator and a phase comparator, wherein the phase comparator has a first input to which the output of the oscillator is connected and a second input to which the clock of the other digital system may be connected, wherein when no clock pulse train is connected to the phase comparator the latter applies to the oscillator a control condition which causes that oscillator to run at its nominal frequency, and wherein when a clock pulse train is connected to the second input of the phase comparator the latter produces a control condition dependent on the relation between that clock pulse train and the oscillator output, which output condition forces the oscillator into a condition in which its output is in synchronism with the clock pulse train applied to said second input.

2. A circuit as claimed in claim 1, wherein the output from the phase comparator is applied to the oscillator, which is a voltage controlled oscillator, via a phase lag filter.

3. A circuit as claimed in claim 1 or 2, wherein the oscillator is a crystal-controlled oscillator.

4. A clock pulse generation circuit substantially as described with reference to the accompanying drawing.