GB1571784A

GB1571784A - Clock regenerators

Info

Publication number: GB1571784A
Application number: GB2459378A
Authority: GB
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1978-05-30
Filing date: 1978-05-30
Publication date: 1980-07-16

Description

(54) IMPROVEMENTS IN OR RELATING TO CLOCK REGENERATORS (71) We, THE PLESSEY COM PANY LIMITED, a British Company, of Vicarage Lane, Ilford, Essex, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to clock regenerators and more particularly to clock regenerators for pulse code modulation transmission systems.

The problem with clock regenerators for P.C.M. transmission systems is that during periods of absence of input signals the clock regenerator at the receiver has no signal to lock on to and can deviate from the correct frequency. When the signal reappears the clock takes a considerable time to re-align to the input signal and during this period of time input information may well be lost.

It is an object of the present invention to provide a clock regenerator which has a reduced acquisition/pull in time.

According to the present invention there is provided a clock regenerator for a pulse code modulation transmission system including a phase locked loop for stabilising the frequency of of a variable frequency oscillator, a standby fixed frequency oscillator, the operating frequency of which is the nominal transmission frequency, a clock recovery circuit for recovering the clock signal from the input received signal, a clock select circuit under the control of the received signal to connect the output of the standby fixed frequency oscillator to the phase locked loop during the absence of a valid input signal and to connect the output of the clock recovery circuit to the phase locked loop during the presence of a valid input signal.

Preferably, the clock regenerator includes a non-valid signal detector which detects the presence of a non-valid received signal and which controls the clock select circuit.

The phase locked loop preferably includes a phase detector the output of which is connected to a filter, in which the output of the filter is used to control the variable frequency oscillator, in which the output of the variable frequency oscillator is connected to a first input of the phase detector and in which the output of the clock select circuit is connected to the second input of the phase detector.

In a preferred embodiment the outputs of the variable frequency oscillator and the clock select circuit are divided before being fed to the phase detector.

Embodiments of the present invention will now be described, by way of example with reference to the accompanying drawing which shows a clock regenerator for a pulse code modulation transmission system in accordance with the present invention.

Referring now to the drawing, the signal R received from the transmission system is fed to an input circuit 10 which preferably comprises an input buffer and amplifier or signal regenerator.

A first output of the circuit 10 is connected to a non-valid signal detection circuit 12 and a second output of the circuit 10 is connected to a clock recovery circuit 14 which provides output pulses in sequence with the incoming received pulse code modulated signals.

The output of the non-valid signal detection circuit 12 is connected as a control input to a clock select circuit 16, one input of which is the output of the clock recovery circuit 14 and the other input is the output of a standby clock generator 18. The output of the clock select circuit 16 is thus either the output of the clock recovery circuit 14 when there is a valid signal present at the input or the output of the standby clock generator 18 when there is no valid input signal.

The phase locked loop is shown with the broken lines and comprises a divide by M divider 20, a phase detector 22, a filter 26 and a divide by N divider 28. The phase detector 22 compares the output of the two dividers 20, 28 and produces a signal which after filtering is used to control the frequency of the oscillator 26.

When a valid signal R is received at the input the signal from the clock recovery circuit is fed to the input of divider 20 and thus controls the frequency and phase of the phase locked loop. When no valid input signal is present the signal from the standby clock 18 is fed to the input of divider 20 and takes over the control of the phase and frequency of the phase locked loop.

The use of the standby clock 18 reduces the phase-locked loop's acquisition time for the following reasons:- i) Since the standby clock frequency is chosen to be within a close tolerance to the nominal frequency of the received signal, the frequency change required of the phaselocked loop variable frequency oscillator upon the application of a valid input signal is minimised.

ii) Some measure of phase alignment between the two phase detector input signals A and B is preserved upon the application of a valid signal if M is greater than unity. The maximum phase discontinuity A) max -produced in signal A during the changeover from the standby to the derived clock is given by: x Amax=± M radians. It will be observed that the larger M the smaller the phase discontinuity. In a conventional circuit the maximum phase discontinuity produced upon the application of an input signal would be +s radians hence an improvements by a factor of M is obtained by the proposed circuit using a standby clock.

WHAT WE CLAIM IS: 1. A clock regenerator for a pulse code modulation transmission system including a phase locked loop for stabilizing the frequency of a variable frequency oscillator, a standby fixed frequency oscillator, the operating frequency of which is the nominal transmission frequency, a clock recovery circuit for recovering the clock signal from the input received signal, a clock select circuit under the control of the received signal, to connect the output of the standby fixed frequency oscillator to the phase locked loop during the absence of a valid input signal and to connect the output of the clock recovery circuit to the phase locked loop during the presence of a valid input signal.

2. A clock regenerator for a pulse code modulation transmission system as claimed in claim 1 in which the clock regenerator includes a non-valid signal detector which detects the presence of a non-valid received signal and which controls the clock select circuit.

3. A clock regenerator for a pulse code modulation transmission system as claimed in claim 1 or claim 2, in which the phase locked loop includes a phase detector the output of which is connected to a filter, in which the output of the filter is used to control the variable frequency oscillator, in which the output of the variable frequency oscillator is connected to a first input of the phase detector and in which the output of the clock select circuit is connected to the second input of the phase detector.

4. A clock regenerator for a pulse code modulation transmission system as claimed in claim 3 in which the output of the variable frequency oscillator and the clock select circuit are connected to respective divider circuits before being fed to the phase detector.

5. A clock regenerator for a pulse code modulation transmission system as described with reference to the accompanying drawing.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

after filtering is used to control the frequency of the oscillator 26.

When a valid signal R is received at the input the signal from the clock recovery circuit is fed to the input of divider 20 and thus controls the frequency and phase of the phase locked loop. When no valid input signal is present the signal from the standby clock 18 is fed to the input of divider 20 and takes over the control of the phase and frequency of the phase locked loop.

The use of the standby clock 18 reduces the phase-locked loop's acquisition time for the following reasons:-

i) Since the standby clock frequency is chosen to be within a close tolerance to the nominal frequency of the received signal, the frequency change required of the phaselocked loop variable frequency oscillator upon the application of a valid input signal is minimised.

ii) Some measure of phase alignment between the two phase detector input signals A and B is preserved upon the application of a valid signal if M is greater than unity. The maximum phase discontinuity A) max -produced in signal A during the changeover from the standby to the derived clock is given by: x Amax=± M radians. It will be observed that the larger M the smaller the phase discontinuity. In a conventional circuit the maximum phase discontinuity produced upon the application of an input signal would be +s radians hence an improvements by a factor of M is obtained by the proposed circuit using a standby clock.

WHAT WE CLAIM IS: 1. A clock regenerator for a pulse code modulation transmission system including a phase locked loop for stabilizing the frequency of a variable frequency oscillator, a standby fixed frequency oscillator, the operating frequency of which is the nominal transmission frequency, a clock recovery circuit for recovering the clock signal from the input received signal, a clock select circuit under the control of the received signal, to connect the output of the standby fixed frequency oscillator to the phase locked loop during the absence of a valid input signal and to connect the output of the clock recovery circuit to the phase locked loop during the presence of a valid input signal.
2. A clock regenerator for a pulse code modulation transmission system as claimed in claim 1 in which the clock regenerator includes a non-valid signal detector which detects the presence of a non-valid received signal and which controls the clock select circuit.
3. A clock regenerator for a pulse code modulation transmission system as claimed in claim 1 or claim 2, in which the phase locked loop includes a phase detector the output of which is connected to a filter, in which the output of the filter is used to control the variable frequency oscillator, in which the output of the variable frequency oscillator is connected to a first input of the phase detector and in which the output of the clock select circuit is connected to the second input of the phase detector.
4. A clock regenerator for a pulse code modulation transmission system as claimed in claim 3 in which the output of the variable frequency oscillator and the clock select circuit are connected to respective divider circuits before being fed to the phase detector.
5. A clock regenerator for a pulse code modulation transmission system as described with reference to the accompanying drawing.