JPH0661988A - Clock riding change circuit - Google Patents

Abstract

PURPOSE:To realize a clock riding change circuit which can be used even when an in-device clock and the clock of a transmission path are the same transmitting source. CONSTITUTION:An ES1 inputs an input data signal 101, operates a clock riding change, and outputs an output data signal 110. Counters 2 and 3 respectively frequency-device an in-device clock 102 before the riding change and a clock 103 for riding change use. When the in-device clock 102 is obtained from the generating source different from that of the clock 103 for riding change use, a phase comparator circuit 4 detects a phase difference between both the clocks, controls a phase control oscillator 10, and adjusts the phase of the clock 103 for the riding change use. When the in-device clock 102 is obtained from the same generating source as the clock 103 for riding change use a phase comparator 5 detects the phase difference, outputs a reset signal 109 to the counter 3, and adjusts the phase of the clock 103 for riding change use. A gate 6 inhibits and switches the reset signal 109 by a reset inhibition signal 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit used in a communication device for transmitting digital signals, and particularly when the data frequency of a transmission line is very high with respect to the clock frequency of a main signal processing circuit in the device. The present invention relates to a clock changing circuit for phase matching.

[0002]

2. Description of the Related Art Presently, the mainstream of the main signal processing circuit in a device in a communication device for transmitting digital signals is a CMOS IC. The maximum operating frequency of the CMOS IC is several tens to 100 MHz, while the frequency of the transmission line reaches several GHz. Therefore, in order to perform accurate phase matching before multiplexing, a circuit for changing the clock in the device to the clock of the transmission line is required.

FIG. 3 is a block diagram of a conventional clock transfer circuit, and FIG. 4 is a timing diagram of FIG. Here, as an example, a 4-bit elastic store (ES)
A clock transfer circuit using a 4-bit counter will be described. The following description refers to FIGS. 4 and 5. The in-device clock signal 102 input from the in-device clock input terminal is input to the first counter 2. The first counter 2 divides the input in-device clock signal 102 and outputs it as output signals 201 and 202 to ES1 and the phase comparison circuit 4, respectively.

On the other hand, the transmission line clock signal 205 from the phase synchronization oscillator, which is the source of the transmission line clock, is divided by the frequency divider 8
The frequency is divided to the same frequency as the in-device clock signal 102 by the
Is input to the counter 3. In the second counter 3, the first
The replacement clock signal 1 input in the same manner as the counter 2 of
03 is divided and E is output signals 204 and 203, respectively.
S1, output to the phase comparison circuit 4.

In ES1, first input data signal 1
01 is converted into four parallel signals by the serial-parallel conversion circuit 8 by the count signal 201 from the first counter 2 (consisting of 201-1 and 201-2 having different division ratios), and the output signal It outputs to the serial-parallel conversion circuit 11 as 206-209. In the serial-parallel conversion circuit 11, the input 4-parallel data signals 206 to 209 are time-division multiplexed by the count signal 204 (consisting of 204-1 and 204-2) from the second counter 3, and the output data of the original serial data. Signal 110
Converted to and output. Since the bit capacity of ES1 is 4 bits, the count signal 20 from the first counter 2
The phase difference between the count signal 204 from the first counter 3 and the count signal 204 from the second counter 3 is normally set to two clocks, and the phase variation range of the transfer clock signal 103 with respect to the input clock signal 102 can be allowed to be two clocks before and after.

As an example of the phase comparison circuit 4, an exclusive OR is used here. Count data 202 from the first counter 2 (1/1 of the internal clock signal 102)
8 clocks) and the count data 203 from the second counter 3 (1/8 clock of the transfer clock signal 103) are compared, and the phase signal 104 is sent to the phase synchronization oscillator 13
Output to. In the phase signal 104, the count data 203 is 1/4 phase shifted from the count data 202, and the in-device clock signal 102 and the transfer clock signal 103
1/4 of the internal clock 102 when the frequencies match
Signal (duty 50%), and becomes "L" level when the count data 202 and the count data 203 have the same phase, and becomes "H" level when they have the opposite phase.

In the phase locked oscillator 13, the phase signal 104 from the phase comparison circuit 4 is input, and the frequency of the output transmission line clock signal 205 is kept until the "L" level and "H" level of the signal become 50%. Fluctuate. By the above operation, the count signal 201 from the first counter 102 and the second signal
The phase difference of the count signal 204 from the counter 103 can always be kept at 2 clocks.

[0008]

As described above, the conventional example is premised on the case where the in-device clock and the transmission line clock are obtained from different clock generation sources. However, there are cases where these are the same source, and in this case as well, as the data processing circuit in the device becomes large-scale, and the buffers and gates for distributing the clock in the device become huge, it becomes difficult to manage the phase, and In many cases, it is necessary to change clocks immediately before multiplexing.

However, in the above-described conventional clock transfer circuit, the counter phase on the device clock side and the counter phase on the transfer clock side are compared, and the result is fed back to the phase synchronization oscillator for generating the transmission line clock. ,
Since the frequency of the phase-synchronized oscillator is controlled, each counter must be in the free-run state, and if the source of the internal clock and the source of the transmission path clock are the same, phase comparison cannot be performed and it cannot be used. There is a problem that there is no.

[0010]

According to another aspect of the present invention, there is provided a clock transfer circuit, in which a data signal according to a first clock is input, and the data is transferred onto a second clock having a phase different from that of the first clock and output. Elastic store, and a first counter that inputs the first clock extracted from the signal of its own station or the transmission line and outputs a first output signal to the input side clock terminal of the elastic store,
A second counter which inputs the second clock generated from a clock generation source of its own station and outputs a first output to a clock terminal on the output side of the elastic store;
A first phase comparison circuit for inputting the second output signal of the counter and the second output signal of the second counter and outputting the second output signal as a phase control signal of the local station clock generation source; A second comparison circuit for inputting the first output signal of the counter and the first output signal of the second counter, and an output of the second phase comparison circuit according to a reset inhibit signal input from the outside. And a gate circuit which prohibits the signal and outputs it as a reset signal of the second counter.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of this embodiment, and FIG. 2 is a timing chart of FIG.

In FIG. 1, an internal clock signal 102
And the transfer clock signal 103 are the same source, but the in-device clock signal 102
A large number of buffers, gates, etc. are provided between the counters to distribute the data processing circuit in the device. On the other hand, the transfer clock signal 103 is directly input from the frequency dividing circuit 11. This is because when the data in the device is multiplexed as the data of the transmission line, the transmission line clock 205 and the transfer clock signal 103 are phase-controlled, so that it is necessary to prevent passage of extra gates, buffers, etc. that cause phase fluctuations. This is because. Also in this case, the difference between the in-apparatus clock and the transfer clock is only the phase, and the frequency does not change.

When the in-apparatus clock signal 102 and the transmission path clock signal 205 are different sources, that is, the same as in FIG. 1 of the conventional example, the reset prohibition signal 105 is prohibited (here, "H" level). , Device clock signal 102
If the phase signal 104 and the phase signal 104 are respectively indicated by dotted lines, the same operation as the conventional circuit can be performed, and thus the description of this part will be omitted.

The case where the in-device clock signal 102 and the transfer clock signal 103 are the same source will be described below. In FIG. 2, the reset prohibition signal 105 always inputs the “L” level, and the gate 6 makes the reset signal 109 from the second phase comparison circuit 5 valid. The output signal 104 of the first phase comparison circuit 4 is not used. The following description refers to FIGS.

In the second phase comparison circuit 5, the count signal 201-2 from the first counter 2 and the second counter 3
And count signals 201-2 and 204-2 (both "0" to "3") are input.
Count value “2” is detected. When both count values “2” match, an “L” pulse is output as the reset signal 109, the count of the second counter 3 is immediately reset, and the count value 204-2 is set to “0”.
By the above operation, the count signal 2 from the second counter 3 with respect to the count signal 201 from the first counter 2
The phase difference of 04 can always be kept within one clock before and after.

[0016]

As described above, the present invention has the effect that the clock hand-over circuit can be used with either the internal clock source and the transmission line clock source which are different from each other or the same source source.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a timing chart of FIG.

[Explanation of symbols]

1 ES 2 1st counter 3 2nd counter 4 1st phase comparison circuit 5 2nd phase comparison circuit 6 Gate 7 Clock transfer circuit 8 Serial / parallel conversion circuit 9 Parallel / direct conversion circuit 10 Oscillator 11 Dividing circuit 101 input data signal 102 in-apparatus clock signal 103 transfer clock signal 104 phase signal 105 reset prohibition signal 106, 107, 201, 202, 203, 204
Count signal 205 Transmission line clock signal

Claims (1)

[Claims] 1. An elastic store for inputting a data signal according to a first clock and transposing and outputting the data for a second clock having a phase different from that of the first clock, and a signal of its own station or a transmission line. The first extracted from
The first counter which inputs the clock of 1st and outputs the first output signal to the clock terminal of the input side of the elastic store, and the second clock which is generated from the clock generation source of its own station, and the first output To the output side clock terminal of the elastic store, the second output signal of the first counter and the second output signal of the second counter are input, and the local clock is input. A first phase comparison circuit that outputs a signal for controlling the phase of a generation source, and a second phase input circuit that inputs the first output signal of the first counter and the first output signal of the second counter. The output signal of the second phase comparison circuit by the comparison circuit and the reset prohibition signal input from the outside is prohibited, and the second phase comparison circuit is prohibited.
And a gate circuit for outputting as a reset signal of the counter.