JP2793351B2 - Timing signal distribution device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a timing signal distribution device that distributes a timing signal to a plurality of signal processing units.

(Prior Art) When a clock signal and a timing signal such as a frequency-divided clock signal obtained by dividing the clock signal are distributed to signal processing circuits formed on a plurality of printed circuit boards via transmission lines on a motherboard, a conventional technique is used. In the above, distribution is performed on a printed circuit board on which a timing signal generation circuit is formed, and each distributed timing signal is transmitted to a plurality of transmission lines formed on a motherboard, so as to be distributed and supplied to a corresponding signal processing circuit. I have.

In this configuration, when the number of distributions is small, the number of transmission lines on the motherboard is also small, and the sending end and the receiving end are 1: 1, so even if the frequency of the clock signal increases to several hundred MHz,
It can be easily matched to the characteristic impedance of the wiring on the motherboard. However, when the number of distributions increases,
The number of transmission lines on the motherboard inevitably increases, and as the frequency of the clock signal increases, the influence between the lines cannot be ignored.

For this reason, a plurality of timing signals having a specific phase relationship, such as a clock signal and a frequency-divided clock signal generated by the timing signal generator, are passed through the motherboard one by one, and each signal processing is conventionally performed. A method of dropping a signal by tapping in a section is adopted. This method is often used for a frame synchronization device such as a synchronous multiplexing device or a cross-connect device.

FIG. 3 shows the configuration of the frame synchronization apparatus. Reference numeral 11 denotes a printed circuit board on which a timing signal generation circuit is formed (hereinafter, referred to as a timing signal generation unit); 12, a mother board on which a transmission line is formed; _{1 to} 13 _N are printed circuit boards each having a signal processing circuit formed thereon (hereinafter, referred to as a signal processing unit), and 14 is formed with a termination circuit for terminating transmission lines on the motherboard 12 by impedance matching. It is a printed circuit board (hereinafter, referred to as an end portion).

N signal processing unit 13 ₁ to 13 _N clock signal used as a reference for operation (hereinafter, referred to as reference clock signal) CK ₁ and frame generation clock signal of the clock signal frequency division data signal (hereinafter, frame CK ₂ is required. Each of the signal processing unit 13 ₁ to 13 _N outputs the processed data signal in accordance with the basic clock signal CK ₁ and the frame signal CK ₂ input.

Timing signal generating section 11 is composed of a basic clock signal and the signal source 11 ₁ to generate the CK _1, a frequency divider 11 ₂ to generate a frame signal CK ₂ the output of the signal source 11 ₁ divides .
The timing signal generator 11 often includes a circuit synchronized with an external high-stability clock source. The frequency of the clock signal CK ₁ hundreds MHz, the frame signal CK ₂ has a repetition frequency of, for example, 8 kHz.

The motherboard 12 takes in the clock signal CK ₁ and the frame signal CK ₂ output from the timing signal generator 11 and sends them to the transmission lines A and B, and taps at N places to N signal processors 13 _{1 to} 13 _N. And sends it to the terminal unit 14. Also,
Captures the data signal output from the signal processing unit 13 ₁ to 13 _N, and sends the terminal end 14 through the transmission line C ₁ -C _N.

Termination unit 14 receives clock signal CK ₁ from motherboard 12,
Captures a frame signal CK _2, terminating taking transmission lines A, B and impedance matching of the motherboard 12. Further, takes in the output data signals of each signal processing unit 13 ₁ to 13 _N from the motherboard C1～C _N, further performs data signal processing. As such data signal processing, for example, in the case of a multiplexing device, multiplexing processing is possible, and in the case of a cross-connect device, switching is conceivable.

Meanwhile, the phase relationship is particular relationship of the clock signal CK ₁ and the frame signal CK ₂ on the motherboard 12, the clock signal CK ₁₁ ~CK _1N inputted to the signal processing units 13 ₁ to 13 _N, the frame signal CK ₂₁ ~ Assuming that CK _2N has the same phase relationship, for example, the time difference between the timings input to the _first signal processing unit 131 and the N-th signal processing unit 13 _N is only the propagation delay on the motherboard 12. Similarly, the signal processing unit
13 ₁ and the time difference between the data signal output of 13 _N same propagation delay. Therefore, the data signals of each signal processing unit 13 ₁ to 13 _N which is input to the terminal portion 14 will be frame phase matches.

However, the clock signal CK ₁ on motherboard 12
And the transmission lines A and B of the frame signal CK ₂ are signal processing units 13 ₁
Taps to ~ 13 _N disturb the characteristic impedance. That is, a form in which a capacitor is added on the transmission line is obtained.

In this case, the matching at the terminating portion 14 cannot be performed well, and the standing waves of the clock signal CK ₁ and the frame signal CK ₂ are superimposed on the motherboard 12. The effect of this standing wave, for example, the phase difference between the clock signal CK _1N to the clock signal CK ₁₁ and the signal processing section 13 _N of the signal processing unit 13 ₁ is not only the propagation delay of the traveling wave.

Since this effect that varies according to the difference in frequency of the standing wave, the clock signal CK ₁ is input to the signal processing unit 13 ₁ to 13 _N
CK _1N and the frame signals CK _{21 to} CK _2N have different phase relationships depending on the position on the motherboard 12. When considered on the frequency axis, the above-described phenomenon appears because the group delay on the motherboard 12 differs depending on the frequency. In order to avoid this, it is conceivable to increase the impedance by inserting a resistor in the tap line.However, if this resistance is increased, the frequency band of the number of taps becomes narrower, so a very large resistor cannot be inserted. As a result, no significant effect is obtained at present.

(Problems to be Solved by the Invention) As described above, in the conventional timing signal distribution device, the phase relationship between a plurality of timing signals that should have a specific phase relationship, such as a clock signal and its divided clock signal, is determined by the motherboard. There is a problem in that when the signal is drawn into each signal processing unit by a tap, it differs depending on the capacity of the transmission line wiring and the location of the tap.

The present invention has been made to solve the above problem, and the phase relationship between various timing signals does not depend on the location of the tap, and the time difference of inputting each timing signal to each board is determined by the progress of the transmission line. It is an object of the present invention to provide a timing signal distribution device determined only by a propagation delay of a wave.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a timing signal distribution device according to the present invention has first and second phase relations having a specific phase relationship with each other.
A timing signal generator for generating a second timing signal, and a motherboard for flowing a timing signal output from the timing signal generator to a transmission line and distributing the timing signal to a plurality of systems by a plurality of taps provided on the transmission line Used in a circuit device including a plurality of signal processing units that input timing signals distributed from the taps of the motherboard and perform signal processing with these timing signals, provided in the timing signal generation unit, Position modulation means for phase-modulating the second timing signal with reference to one timing signal and supplying the modulated signal to the motherboard; The modulated signal is supplied from the tap of the second timing signal, and the second timing signal is Constituted by and a phase demodulation means for regulating.

(Operation) In the timing signal distribution device having the above configuration, the timing signal generator side modulates the phase of the second timing signal based on the first timing signal, and distributes the phase modulation signal from the tap of the motherboard on the signal processing side. By demodulating the second timing signal from the modulated signal, the impedance of the tap on the motherboard is increased, and the phase relationship of the plurality of timing signals to be drawn into each signal processing unit can be made all constant. The propagation delay between them is only the propagation delay of the traveling wave.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1 and FIG. However, in FIG. 1, the same portions as those in FIG. 3 are denoted by the same reference numerals, and different portions will be mainly described here.

Figure 1 is shows the configuration, it is further added the phase modulation circuit 11 ₃ to the timing signal generator 11, a frequency divider 11 ₂
By phase modulating the frame signal CK ₂ obtained in the clock signal CK _1, and outputs a modulated frame signal CK ₂ '. These clock signals CK ₁ and the modulation frame signal CK ₂ 'transmission lines A on the motherboard 12, is sent to B, it is supplied to the signal processing unit 13 ₁ to 13 _N through N taps, end It is supplied to the unit 13 and terminated.

On the other hand, the signal processing unit 13 ₁ to 13 _N phase demodulation circuit 13 _11-3
N1 is added, so as to demodulate the frame signal CK ₂ 'being modulated by the timing signal generator 11 the clock signal CK _1.

The phase modulation circuit 11 _3, as shown in FIG. 2, can be realized by taking the exclusive OR of the clock signal CK ₁ and the frame signal CK _2. Conversely, the phase demodulation circuits 13 _{11 to} 13
_N1 can be realized by taking the exclusive OR of the modulated frame signal CK ₂ 'and the clock signal CK _1. Here, the spectral distributions of the clock signal CK ₁ and the modulated frame signal CK ₂ ′ are almost the same, and the modulated frame signal CK ₂ ′ only spreads by the amount of the phase modulation.

As described above, increasing the impedance of the taps of the motherboard 12, the passband of the tap input of the signal processing unit 13 ₁ to 13 _N is limited. However, even with the frequency characteristic to the tap unit, a clock signal CK ₁ and the modulated frame signal C
Since K ₂ ′ has almost the same frequency spectrum and is close to a single spectrum, no distortion occurs and linear loss occurs.

Therefore, the timing signal distributing apparatus according to the arrangement, it is possible to increase the impedance of the tap unit, and all constant phase relationship of the modulated frame signal CK ₂ 'and the clock signal CK ₁ pulled into the signal processing units 13 ₁ to 13 _N can do. In addition, it is possible to maintain good matching at the terminating section 14, and to make the propagation delay between taps only the propagation delay of the traveling wave.

[Effects of the Invention] As described above, according to the present invention, the phase relationship between various timing signals does not depend on the location of the tap, and the time difference between the timing signals input to each board is a traveling wave traveling through the transmission line. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a timing signal distribution device according to the present invention. FIG. 2 is a timing waveform diagram for explaining the operation of the phase modulation circuit and the phase demodulation circuit of the embodiment. FIG. 1 is a block diagram showing an example of a conventional timing signal distribution device. 11 timing signal generator, 11 ₁ clock signal source, 11 ₂ frequency divider, 11 ₃ phase modulator circuit, 12 motherboard, 13 _{1 to} 13 _N signal processor 13 ₁₁ ~ 13 _N1 …… Phase demodulation circuit, 14 …… Terminal, CK ₁ …… Clock signal, CK ₂
…… Frame signal, A …… Clock signal transmission line, B
…… Frame signal transmission line, C _{1 to} C _N …… Data transmission line.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/04 G06F 1/04 301

Claims (3)

(57) [Claims] A first and a second phase having a specific phase relationship with each other.
A timing signal generator for generating a timing signal of
A timing signal output from the timing signal generator is sent to a transmission line, and a plurality of taps provided on the transmission line distribute a plurality of taps to a motherboard, and a timing signal distributed from each of the taps of the motherboard. A plurality of signal processing units for inputting and performing signal processing with these timing signals, the signal processing unit being provided in the timing signal generation unit,
Phase modulation means for phase-modulating the second timing signal on the basis of the timing signal of the second timing signal, and providing the modulated signal to the motherboard; A timing signal distribution device, comprising: a phase demodulator that receives the modulated signal from a tap and demodulates the second timing signal. 2. The method according to claim 1, wherein the first timing signal is a basic clock signal of the signal processing unit, and the second timing signal is a frame signal obtained by dividing the frequency of the basic clock signal. The timing signal distribution device according to claim 1, wherein 3. The phase modulating means is configured to take an exclusive OR of the basic clock signal and the frame signal, and the phase demodulating means is phase-modulated by the basic clock signal and the phase modulating means. 3. The timing signal distribution device according to claim 2, wherein the timing signal distribution device is configured to perform a non-OR operation with a modulation frame signal.