JPS62266914A - Phase comparator - Google Patents

Abstract

PURPOSE:To obtain a phase comparator having a triangle phase comparison characteristic with respect to an input signal where the level converting point appears periodically by outputting a sent signal from an exclusive OR gate as a signal representing the phase difference of the 1st and 2nd input signals. CONSTITUTION:A frequency division counter 10 is forcible reset at a level conversion point of an input signal 1, applies 1/N frequency division to a clock signal and sends a signal having a level conversion point periodically at nearly T/4 each. said signal is given to one input of the exclusive OR gate 11. An input signal 2 is a signal having the level conversion point periodically at a period T/2 substantially, that is, at nearly T/4 each and is inputted to another input of the gate 11. The gate 11 generates a signal having a pulse leading for a period of phase deviation between a signal sent from the frequency division counter 10 and the input signal 2. That is, an output signal having a pulse width equal to the phase difference of the frequency division signals of the input signals l', 2' is obtained to attain the triangle phase comparison characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to phase comparators, particularly for use in phase-locked loop circuits and the like.

[Conventional technology]

Conventionally, exclusive OR (EX-OR) gates have been widely used as digital phase comparators in phase-locked loop circuits and the like. If signal level conversion points appear approximately periodically for the two signals input to the two input ends of the EX-OR gate, a triangular phase comparison characteristic can be obtained.

[Problem that the invention seeks to solve]

However, the conventional phase comparator using an EX-OR gate does not have the same level transition point when one of the two input signals does not appear periodically, as in the case where one of the two input signals has a biphase code format, for example. There is a problem in that even if used as is, the desired phase comparison characteristics cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase comparator that solves the above-mentioned problems and can obtain triangular phase comparison characteristics for input signals in which level change points do not appear periodically.

[Means for solving problems]

The phase comparator of the present invention includes a frequency division counter that divides a clock signal having a predetermined period while resetting at the level conversion point of a first input signal in which the appearance of the level conversion point is not periodic; an exclusive OR gate, the input terminal of which is supplied with the output signal of the frequency dividing counter, and the other input terminal of which is supplied with a second input signal in which the appearance of the level conversion point is periodic; The output signal of the exclusive OR gate is output as a signal indicating the phase difference between the first and second input signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a block diagram showing one embodiment of the present invention and a timing chart illustrating its operation, respectively. The input signal (1) given to the phase comparator 1 in FIG.
This is a signal in which level change points appear not periodically, and the input signal (2) is a signal in which level change points appear periodically. FIG. 2B shows an example in which the input signal (1) is a biphase signal. In this case, at the timing shown by the solid line arrow for each period T of the pi-phase code,
A level change point always appears. However, at the center point of the code period, a level change point may or may not appear (as indicated by the dashed arrow).

Such an input signal (1) is applied to the reset terminal of the divide-by-5 counter 10 to reset the divider counter 10 at the level conversion point. The clock signal applied to the clock input terminal C of the frequency division counter 10 is as follows.

This is a clock signal having a period set to 1/2N of the code period T of the input signal (1) (however, a natural number equal to the frequency division ratio of the N-fold frequency division counter 10). frequency division counter 101d,
After being forcibly reset at the level conversion point of the input signal (1) as described above, the clock signal is frequency-divided by N to send out a signal in which the level conversion point appears periodically approximately every T/4. The output signal of the frequency division counter 10 is an exclusive OR (
EX-OR) is applied to one input terminal of the gate 11.

The input signal (2) applied to the other input terminal of the EX-OR gate 11 is a signal having a period substantially equal to T/2, that is, a level change point appears periodically approximately every T/4. This is a signal to The EX-OR gate 11 generates a signal in which a pulse rises only during a phase shift period between the output signal of the frequency dividing counter 10 and the input signal (2),
Send it as an output signal.

The pulse width of the output signal is determined by the phase of the level conversion point of the input signal (1) shown by the solid arrow in Figure (b) and the phase of the level conversion point of the input signal (2) which is closest to this point. Equal to the difference from the phase. That is, an output signal having a pulse width equal to the phase difference between the input signal (1) and the frequency-divided signal of the input signal (2) can be obtained, and therefore a triangular phase comparison characteristic can be realized.

As described above, in this embodiment, one input terminal of the EX-OR gate 11 receives the input signal (
1) With a simple circuit configuration that gives
It is possible to compare the phases of an input signal (1), in which level change points do not appear periodically, such as a signal with an input signal, and an input signal (2), in which level change points appear periodically, using the triangular phase comparison characteristic. .

〔Effect of the invention〕

As explained above, the present invention has the advantage that it is possible to realize a phase comparator having triangular phase comparison characteristics for input signals in which level change points do not appear periodically.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a block diagram and a timing diagram, respectively, showing an embodiment of the present invention. 1... Phase comparison circuit, 10... Frequency division counter. 11...Exclusive OR (EX-OR) gate. Pah Agent Orator Uchihara Hi□°；・－―”、N

Claims (1)

[Claims] a frequency division counter that divides a clock signal having a predetermined period while resetting at the level conversion point of a first input signal in which level conversion points do not appear periodically; an exclusive OR gate to which a second input signal in which the appearance of level conversion points is periodic is supplied to the other input terminal, and the exclusive OR gate A phase comparator characterized in that the output signal is output as a signal indicating a phase difference between the first and second input signals.