JPS6331404U - - Google Patents
Info
- Publication number
- JPS6331404U JPS6331404U JP12614186U JP12614186U JPS6331404U JP S6331404 U JPS6331404 U JP S6331404U JP 12614186 U JP12614186 U JP 12614186U JP 12614186 U JP12614186 U JP 12614186U JP S6331404 U JPS6331404 U JP S6331404U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- selection
- rom
- terminal
- sequencer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例によるシーケンサ
ーの論理回路図、第２図は従来のシーケンサーの
論理回路図、第３図は、第１図の動作を説明する
ためのクロツク信号のタイミングチヤート図、第
４図は第２図の動作を説明するためのクロツク信
号のタイミングチヤート図である。
図中、１はラツチ付セレクター（選択回路）、
２はＲＯＭ、３はラツチ回路、４はＲＯＭである
。なお、図中、同一符号は同一、又は相当部分を
示す。
FIG. 1 is a logic circuit diagram of a sequencer according to an embodiment of this invention, FIG. 2 is a logic circuit diagram of a conventional sequencer, and FIG. 3 is a timing chart of a clock signal to explain the operation of FIG. 1. , FIG. 4 is a timing chart of clock signals for explaining the operation of FIG. 2. In the figure, 1 is a selector with a latch (selection circuit),
2 is a ROM, 3 is a latch circuit, and 4 is a ROM. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
択回路からの選択出力がアドレス入力端子に接続
されたＲＯＭと、このＲＯＭのデータ端子と接続
されたラツチ回路を有し、このラツチ回路の出力
が上記ＲＯＭの別のアドレス端子と、上記選択回
路の選択入力端子に接続される事を特徴とするシ
ーケンサー回路。 (2) 選択回路とラツチ回路にそれぞれ供給され
るクロツク信号は周期が等しく、所定時間だけ位
相がずれていることを特徴とする実用新案登録請
求の範囲第１項記載のシーケンサー回路。[Claims for Utility Model Registration] (1) A selection circuit that selects a plurality of signals, a ROM in which the selection output from this selection circuit is connected to an address input terminal, and a latch circuit connected to a data terminal of this ROM. A sequencer circuit comprising: an output of the latch circuit is connected to another address terminal of the ROM and a selection input terminal of the selection circuit. (2) The sequencer circuit according to claim 1, wherein the clock signals respectively supplied to the selection circuit and the latch circuit have the same period and are shifted in phase by a predetermined time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12614186U JPS6331404U (en) | 1986-08-19 | 1986-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12614186U JPS6331404U (en) | 1986-08-19 | 1986-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331404U true JPS6331404U (en) | 1988-03-01 |
Family
ID=31019668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12614186U Pending JPS6331404U (en) | 1986-08-19 | 1986-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331404U (en) |
-
1986
- 1986-08-19 JP JP12614186U patent/JPS6331404U/ja active Pending
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