JPS6284234U - - Google Patents
Info
- Publication number
- JPS6284234U JPS6284234U JP1985174571U JP17457185U JPS6284234U JP S6284234 U JPS6284234 U JP S6284234U JP 1985174571 U JP1985174571 U JP 1985174571U JP 17457185 U JP17457185 U JP 17457185U JP S6284234 U JPS6284234 U JP S6284234U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- frequency dividing
- basic
- output
- selection signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Details Of Television Systems (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
第１図の動作説明に供するタイムチヤート、第３
図は従来例の回路図、第４図は第３図の従来例の
動作説明に供するタイムチヤートである。
１〜３…第１〜第３分周回路群、４〜９…第１
〜第６Ｄ―フリツプフロツプ（分周回路）、１２
…ゲート手段。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of Fig. 1, and Fig. 3 is a time chart for explaining the operation of Fig. 1.
The figure is a circuit diagram of a conventional example, and FIG. 4 is a time chart for explaining the operation of the conventional example of FIG. 1 to 3...first to third frequency dividing circuit group, 4 to 9...first
~6th D-flip-flop (frequency divider circuit), 12
…gate means.
Claims (1)
周比で分周した各分周クロツクの内から所望のク
ロツクを選択して出力するクロツク選択回路にお
いて、 基本クロツクをそれぞれ分周して出力する複数
の分周回路群と、 前記各分周回路群の出力、前記基本クロツクお
よび前記所望のクロツクを選択するための選択信
号が与えられ、これらに基づいて前記所望のクロ
ツクを形成出力するゲート手段とを備え、 前記各分周回路群は、複数段の分周回路からそ
れぞれ構成されるとともに、前記各分周回路の分
周動作は前記選択信号によつて制御されることを
特徴とするクロツク選択回路。[Claims for Utility Model Registration] In a clock selection circuit that selects and outputs a desired clock from among a basic clock and each divided clock obtained by dividing the basic clock at different frequency division ratios, and a selection signal for selecting the output of each of the frequency dividing circuit groups, the basic clock, and the desired clock, and the desired clock is formed based on these. and a gate means for outputting an output, each of the frequency dividing circuit groups being composed of a plurality of stages of frequency dividing circuits, and the frequency dividing operation of each of the frequency dividing circuits being controlled by the selection signal. Features a clock selection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985174571U JPS6284234U (en) | 1985-11-13 | 1985-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985174571U JPS6284234U (en) | 1985-11-13 | 1985-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284234U true JPS6284234U (en) | 1987-05-29 |
Family
ID=31113078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985174571U Pending JPS6284234U (en) | 1985-11-13 | 1985-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284234U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473386A (en) * | 1987-09-14 | 1989-03-17 | Seiko Epson Corp | Clock signal generator |
-
1985
- 1985-11-13 JP JP1985174571U patent/JPS6284234U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473386A (en) * | 1987-09-14 | 1989-03-17 | Seiko Epson Corp | Clock signal generator |
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