JPS6413826U - - Google Patents
Info
- Publication number
- JPS6413826U JPS6413826U JP10801987U JP10801987U JPS6413826U JP S6413826 U JPS6413826 U JP S6413826U JP 10801987 U JP10801987 U JP 10801987U JP 10801987 U JP10801987 U JP 10801987U JP S6413826 U JPS6413826 U JP S6413826U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock
- multiplexing
- generating means
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000926 separation method Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Time-Division Multiplex Systems (AREA)
Description
第１図および第２図は、それぞれ本考案による
デイジタル信号中継回路の第１および第２の実施
例を示すブロツク図である。第３図は、第１図お
よび第２図において多重数Ｎ＝４に対する多重回
路の動作を示すタイムチヤートである。第４図は
、従来技術によるデイジタル信号中継回路の実例
を示すブロツク図である。第５図は、第４図にお
ける多重数Ｎ＝４に対する多重回路の動作を示す
タイムチヤートである。
１，２１，４１……分離回路、２，２２，４２
……Ｄ／Ｉ回路、３，２３，４３……多重回路、
４，２４，４４……計数回路、５……シフトレジ
スタ、２５……リング計数回路、２６……デユー
テイ比調整回路、ａ〜ｈ，ｈ′，ｋ，２ａ〜２ｈ
，２ｈ′，２ｋ′，４ａ〜４ｄ，４ｇ，４ｈ，４
ｈ′，４ｊ……信号。
1 and 2 are block diagrams showing first and second embodiments of a digital signal relay circuit according to the present invention, respectively. FIG. 3 is a time chart showing the operation of the multiplex circuit for the multiplex number N=4 in FIGS. 1 and 2. FIG. 4 is a block diagram showing an example of a digital signal relay circuit according to the prior art. FIG. 5 is a time chart showing the operation of the multiplex circuit for the multiplex number N=4 in FIG. 1, 21, 41...separation circuit, 2, 22, 42
...D/I circuit, 3, 23, 43...Multiple circuit,
4, 24, 44...Counting circuit, 5...Shift register, 25...Ring counting circuit, 26...Duty ratio adjustment circuit, a to h, h', k, 2a to 2h
, 2h', 2k', 4a-4d, 4g, 4h, 4
h', 4j...signal.
Claims (1)
に分離するための分離回路と、前記多重によつて
生成された伝送信号の一部を抜出すか、あるいは
新たに別の信号を挿入するためのＤ／Ｉ回路と、
いつたん分離した前記低位デイジタル信号を再び
多重するための多重回路と、前記分離回路に与え
る低速クロツクを生成するための計数回路と、前
記多重回路に与える多相クロツクを生成するため
のクロツク生成手段と、前記計数回路の入力クロ
ツクを同時に前記クロツク生成手段のシフトクロ
ツクとして与え、且つ、前記計数回路の分周出力
を前記クロツク生成手段の入力端子へ与えるため
の信号路とを具備して構成したことを特徴とする
デイジタル信号中継回路。 A separation circuit for separating an input signal into a plurality of low-order digital signals before multiplexing, and a D for extracting a part of the transmission signal generated by the multiplexing or inserting a new signal. /I circuit,
a multiplexing circuit for multiplexing the separated low-order digital signals again; a counting circuit for generating a low-speed clock to be applied to the separating circuit; and a clock generating means for generating a multiphase clock to be applied to the multiplexing circuit. and a signal path for simultaneously applying the input clock of the counting circuit as a shift clock to the clock generating means, and applying the frequency-divided output of the counting circuit to the input terminal of the clock generating means. A digital signal relay circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10801987U JPH0546361Y2 (en) | 1987-07-14 | 1987-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10801987U JPH0546361Y2 (en) | 1987-07-14 | 1987-07-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413826U true JPS6413826U (en) | 1989-01-24 |
| JPH0546361Y2 JPH0546361Y2 (en) | 1993-12-03 |
Family
ID=31342959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10801987U Expired - Lifetime JPH0546361Y2 (en) | 1987-07-14 | 1987-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0546361Y2 (en) |
-
1987
- 1987-07-14 JP JP10801987U patent/JPH0546361Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0546361Y2 (en) | 1993-12-03 |
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