JPH0320558U - - Google Patents
Info
- Publication number
- JPH0320558U JPH0320558U JP8081089U JP8081089U JPH0320558U JP H0320558 U JPH0320558 U JP H0320558U JP 8081089 U JP8081089 U JP 8081089U JP 8081089 U JP8081089 U JP 8081089U JP H0320558 U JPH0320558 U JP H0320558U
- Authority
- JP
- Japan
- Prior art keywords
- bit rate
- circuit
- latch circuits
- bits
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Time-Division Multiplex Systems (AREA)
Description
第１図はこの考案に係るデイジタル信号分離回
路の一実施例を示すブロツク構成図、第２図は第
１図の各部のタイミングチヤート、第３図は従来
のデイジタル信号分離回路を示すブロツク構成図
である。
１４……ｎビツトのシフトレジスタ、１５……
シフト信号、１６……カウンタ、１７，１８およ
び１９……ｆ０／ｍ×ｎクロツク、２０，２１お
よび２２……ラツチ回路、２３，２４および２５
……情報信号、２６，２７および２８……Ｐ／Ｓ
回路。
FIG. 1 is a block configuration diagram showing an embodiment of the digital signal separation circuit according to this invention, FIG. 2 is a timing chart of each part of FIG. 1, and FIG. 3 is a block configuration diagram showing a conventional digital signal separation circuit. It is. 14...n-bit shift register, 15...
Shift signal, 16... Counter, 17, 18 and 19... f 0 /m×n clock, 20, 21 and 22... Latch circuit, 23, 24 and 25
...Information signal, 26, 27 and 28...P/S
circuit.
Claims (1)
多重されたビツトレートｆ０のデイジタル信号を
ｎビツト単位にｍ本に分離するデイジタル信号分
離回路において、ビツトレートｆ０の入力信号を
ｎビツトシフトするシフトレジスタと、このシフ
トレジスタの出力をｆ０／ｍ×ｎの周波数で固定
するｎ本分のｍ個のラツチ回路と、このラツチ回
路のｎ本の出力をビツトレートｆ０／ｍの直列信
号に多重するｍ個の並列−直列変換回路と、ラツ
チ回路に渡すｆ０／ｍ×ｎのｍ本のクロツクを目
的の位相に生成するカウンタ回路とを備えたこと
を特徴とするデイジタル信号分離回路。 In a digital signal separation circuit that separates m serially multiplexed digital signals of bit rate f0 into m pieces of n-bit units with continuous n bits as information units, a shift register that shifts an input signal of bit rate f0 by n bits is used. , m latch circuits for n latch circuits that fix the output of this shift register at a frequency of f 0 /m×n, and m that multiplexes the n outputs of these latch circuits into a serial signal with a bit rate f 0 /m. 1. A digital signal separation circuit comprising: parallel-to-serial conversion circuits; and a counter circuit that generates m clocks of f 0 /m×n to be passed to a latch circuit in a desired phase.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8081089U JPH0320558U (en) | 1989-07-11 | 1989-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8081089U JPH0320558U (en) | 1989-07-11 | 1989-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320558U true JPH0320558U (en) | 1991-02-28 |
Family
ID=31626192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8081089U Pending JPH0320558U (en) | 1989-07-11 | 1989-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320558U (en) |
-
1989
- 1989-07-11 JP JP8081089U patent/JPH0320558U/ja active Pending
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