JPS6249351U

JPS6249351U -

Info

Publication number: JPS6249351U
Application number: JP12799586U
Authority: JP
Priority date: 1986-08-22
Filing date: 1986-08-22
Publication date: 1987-03-26

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は本考案の一実施例を示す回路図、第３図
は本考案の一実施例の動作タイミングチヤートを
示す。１０……ケーブルドライバ、２０……ケーブル
レシーバ、３０……ビツト位相補正回路、３１…
…ビツト遅延回路、３２……ビツト位相比較回路
、３３……ビツト同期化回路、４０……フレーム
位相補正回路、４１……フレーム遅延回路、４２
……フレーム位相比較回路、４３……フレーム同
期化回路、５０……自装置内クロツク、５１……
自装置内フレームパルス、６０……同期化データ
、７０，７１，７２……遅延回路、７３，７４，
７５……フリツプフロツプ、７６，７７，７８…
…優先選択ゲート、７９，８０，８１……ＡＮＤ
ゲート、８２，８６……ＯＲゲート、８３，８４
，８５……ＡＮＤゲート、８７，８８……シフト
レジスタ、８９，９０，９１，９３，９４，９５
……フリツプフロツプ、９２，９６，９７，９８
……ＡＮＤゲート、９９……ＯＲゲート。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an operation timing chart of the embodiment of the present invention. 10... Cable driver, 20... Cable receiver, 30... Bit phase correction circuit, 31...
...Bit delay circuit, 32...Bit phase comparison circuit, 33...Bit synchronization circuit, 40...Frame phase correction circuit, 41...Frame delay circuit, 42
... Frame phase comparison circuit, 43 ... Frame synchronization circuit, 50 ... Clock within own device, 51 ...
Frame pulse within own device, 60...Synchronization data, 70, 71, 72...Delay circuit, 73, 74,
75...flip flop, 76, 77, 78...
...Priority selection gate, 79, 80, 81...AND
Gate, 82, 86...OR gate, 83, 84
, 85...AND gate, 87, 88...Shift register, 89, 90, 91, 93, 94, 95
...flip flop, 92, 96, 97, 98
...AND gate, 99...OR gate.

Claims

[Claims for Utility Model Registration] A receiver that separates a digital signal from a digital transmission line into data, a frame pulse, and a clock; a bit delay circuit that provides a plurality of types of identical delays to each of the data and the frame pulse; a bit phase comparator circuit that compares the phase of a delay clock that has been given multiple types of delays that are the same as those of the data and the frame pulse and a clock within the device itself and outputs a delayed clock that has a matched phase; and the bit delay circuit. a bit phase correction circuit having a bit synchronization circuit that achieves bit synchronization using each of a plurality of types of delayed data and a plurality of types of delayed frame pulses from the bit phase comparison circuit and the delayed clock of the same phase from the bit phase comparison circuit; a frame delay circuit that delays synchronized data from the bit synchronization circuit in multiple types in bit units;
The synchronization frame pulse from the bit synchronization circuit is given multiple types of delays that are the same as the synchronization data, and the phases of the synchronization frame pulse and the frame pulse within the device are compared, and a synchronization frame pulse with a matching phase is obtained. A frame having a frame phase comparison circuit to output, and a frame synchronization circuit that performs frame synchronization using a plurality of types of synchronization data from the frame delay circuit and synchronization frame pulses of the matched phase from the frame phase comparison circuit. A delay type phase correction device comprising: a phase correction circuit;