JPS6192058A - Time slot synchronizing circuit - Google Patents

Abstract

PURPOSE:To make time slot synchronization of channel output data possible with a simple constitution by providing the first shift register to which output data is inputted and the second shift register to which a frame pulse is inputted and leading out data from gate means which gate corresponding parallel outputs. CONSTITUTION:Channel output data (D) from a line storage part 1 is inputted to an 8-bit shift register 2, and a frame pulse (B) supplied to the line storage part 1 is transmitted as a frame pulse (C). This frame pulse (C) is inputted to the shift register 3. The 8-bit parallel output of the shift register 3 is latched in a latch circuit 4 by the timing determined by the frame pulse (C). This 8-bit parallel latch output becomes a gate signal of a gate circuit 5 to form an 8-bit parallel output of the shift register 2. This gate output (F) is latched by a latch circuit 6 in the output stage, and this latch output becomes channel output data.

Description

TECHNICAL FIELD The present invention relates to a time slot synchronization circuit, and more particularly to a time slot synchronization circuit for achieving phase synchronization between a time slot and channel output data in a digital exchange.

In the digital exchange, it is necessary to synchronize the channel output data sent from the line accommodation section with the time slot.

Therefore, a time slot synchronization circuit is required, but due to variations in the propagation delay times of the circuit elements, accurate synchronization may not be achieved, and trying to compensate for this has the disadvantage of complicating the circuit configuration. be.

Purpose of the Invention The purpose of the present invention is to synchronize channel output data to time slots using an extremely simple circuit configuration.
The time slot synchronization circuit according to the present invention is directed to a time slot synchronization circuit that synchronizes the phase of output data sent from a line accommodation section and frame pulses also sent out from this line accommodation section. It is characterized by a first shift register that receives output data and sequentially shifts this data using a highway clock, and a second shift register that receives the frame pulse and sequentially shifts this data using a highway clock.
a shift register, latch means for latching the parallel outputs of the second shift register by frame pulses, and gate means for gating the corresponding parallel outputs of the first shift register by the parallel outputs of the latch means. The reason is that the data is derived from the gate output.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which channel output data (D) from a line accommodation section 1 is input to an 8-bit shift register 2, and is also supplied to this line accommodation section 1. The frame pulse (B) passed through a number of circuits within the line accommodation section 1 is sent out again from the line accommodation section 1 as a frame pulse (C). This transmitted frame pulse (C) is input to the shift register 3. The two shift registers 2 and 3 are configured to perform a shifting operation using a highway cloter (A).

The 8-bit parallel outputs of the shift register 3 are each latched into a latch circuit 4 according to the latch timing determined by the frame pulse (C). This 8-bit parallel latch output serves as a gate signal for the gate circuit 5, and gates the 8-bit parallel outputs of the shift register 2, respectively. This gate output (F) is latched by the latch circuit 6 at the output stage, and this latch output becomes channel output data.

Figures 2 (A) to (F) show the signals of each part of the block in Figure 1 (
Waveform diagrams A) to (F) are shown correspondingly. Here, since one time slot in a digital exchange consists of 8 clock pulse cycles, the phase shift of the channel output data is latched with the frame pulse indicating the division of one time slot, and the channel output data is converted into the phase shift pattern. The block is latched to synchronize the channel output data with the time slot.The operation of the block shown in FIG. 1 will be described below with reference to the operating waveforms shown in FIG.

The phase relationship between the highway clock and the frame pulse supplied to the line accommodation section 1 is shown in (A) of the figure.

As shown in (B), one cycle of the frame pulse is eight cycles of the clock pulse, and this indicates one time slot. The frame pulse that has passed through the line accommodation section 1 is delayed within the line accommodation section 1 and has a phase as shown in FIG. 3(C). The channel output data from the line accommodating section 1 is also delayed to the same extent as the frame pulse, as shown in Figure (D). In addition, although the frame pulse (C) and the channel output data (D) are shown to be synchronized in phase in the figure for simplicity, in reality, the phase relationship between the two is random, and the phase relationship between the two is random. The purpose of the present invention is to synchronize the phases of the two.

Therefore, first, when the frame pulse (C) is taken into the shift register 3 at the timing of the clock pulse a□, the output of this shift register 3 becomes as shown in (E), and at the same time, the first of the channel output data is input by this pulse aO. The O bit is also taken into shift register 2. Therefore,
At the output of the gate 5, O-bit output data is generated as shown in (F) at the timing of synchronization a□, that is, at the timing synchronized with the frame pulse.

Similarly, the next 1-bit data is gated and output in synchronization with the timing of the second clock pulse a1. Thereafter, in the same manner, 2 to 7 bit data are sequentially gated and output at each timing of the 7 frame pulses a2 to a7, and become output data via the latch circuit 6 at the next stage.

In this way, the channel output data will be output in exact synchronization with the time slots.

Effects of the Invention According to the present invention, the amount of hardware is substantially TT
There is an advantage that accurate time slot synchronization of channel output data is possible with a simple configuration using only a few L (transistor-transistor-logic) circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing waveform diagram showing the operation of the blocks in FIG. 1. Explanation of symbols of main parts 1...Line accommodation section

Claims (1)

[Claims] A time slot periodic circuit that synchronizes the phase of output data sent from a line accommodation section with a frame pulse also sent out from this line accommodation section, which receives the output data as input and sequentially shifts this data using a highway clock. a first shift register; a second shift register that receives the frame pulse and sequentially shifts the frame pulse according to the highway clock; and a latch means that latches parallel outputs of the second shift register with the frame pulse, respectively. and gate means for gating corresponding parallel outputs of the first shift register by the parallel outputs of the latch means, and data is derived from the gate outputs. .