KR20000039962A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: A Phase locked loop(PLL) circuit is provided to realize phase lock during 1 to 2 clocks though input clocks are locked using a plurality of reference clocks. CONSTITUTION: A PLL circuit comprises RS flip-flops(202) and D flip-flops(216) respectively consisting one locked signal generation module. Adjacent two reference clocks(K0,K1) are input to the RS flip-flop(202), the output of which is input to the D flip-flop(216). The D flip-flop is operated by an input clock(CLK_IN) to generate a phase detection signal(S0). The PLL has the same number of the module as that of the reference clock(K0-/K3) to detect the section which the phase of the input clock belongs to.

Description

Phase locked loop circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly, to a phase locked loop circuit for comparing an input clock with a plurality of reference clocks, respectively, and synchronizing with a reference clock of a closest phase.

In general, a phase locked loop circuit compares an input clock with a plurality of reference clocks having the same phase difference, and synchronizes them with a reference clock of a phase closest to the input clock. To implement this, first, a reference clock generator, a multiplexer for selecting two neighboring reference clocks among a plurality of generated reference clocks, and a mixer for mixing phases of the selected two reference clocks are needed.

1 is a diagram showing the configuration and operation of a conventional phase-locked loop circuit. FIG. 1A is a diagram illustrating a concept of a reference clock generation, FIG. 1B is a block diagram illustrating a synchronization signal generator, and FIG. 1C is a diagram illustrating operation characteristics of a synchronization signal generator.

As shown in FIG. 1A, four divisions of one reference clock can generate eight reference clocks having a phase difference of 45 degrees. This is achieved by connecting eight delay means in series to produce a 45-degree phase delay, passing one reference clock through these eight delay means, and taking out the output of each delay means. Reference clocks K0 to K7 can be generated.

The reference clocks K0 to K3 are reference clocks with phases of 0 degrees, 45 degrees, 90 degrees, and 135 degrees, respectively. If the phases of the four reference clocks K0 to K3 are reversed (that is, the phase of 180 degrees is added) Four other reference clocks / K0 to / K3 having phases of 180 degrees, 225 degrees, 270 degrees, and 315 degrees can be obtained.

In FIG. 1 (a), an area labeled S0 to S7 means an area between two neighboring reference clocks. In order to synchronize the phase of the input clock with the phase of the reference clock, it is first necessary to detect which of these eight phase regions belongs.

FIG. 1 (b) is a block diagram of a sync signal generator for generating a sync signal by detecting which area of FIG. 1 (a) belongs to. Eight reference clocks K0 to / K3 are input to the multiplexer 102, and two neighboring reference clocks Ki (Ki + 1) are selected by the selection signal SEL. The two selected reference clocks Ki (Ki + 1) are input to the mixer 104. In the mixer 104, the phases of the two reference clocks Ki (Ki + 1) inputted are calculated according to a specific function to generate a synchronization signal Kout having the same phase as the input clock.

The function applied to the two reference clocks Ki (Ki + 1) in the mixer 104 may be as follows.

K _out = (1-x) K _i + x K _i 0x1

In Equation 1 above, x is a value that constantly changes within a range greater than 0 and less than 1 to determine a phase of a clock that is actually synchronized to an input clock. As the value of x changes, the value of Kout also changes, which is shown in FIG. The smaller the value of x is, the closer the phase is to K0, which is 0 degrees. On the contrary, the larger the value of x is, the closer the phase is to K1, which is 45 degrees.

The multiplexer 102 selects two neighboring reference clocks Ki (Ki + 1), and the result value according to a specific function in the mixer 104 for the selected two reference clocks Ki (Ki + 1). In order to obtain Kout, the above-described operation must be repeated for all reference clocks input to the multiplexer 102. That is, when the phase of the input clock is not in the region between K0 and K1, and is between / K3 and K0 (S7 in Fig. 1 (a)), all eight detection operations must be repeated, and the locking time ) Takes eight clocks.

Accordingly, an object of the present invention is to enable phase synchronization during one to two clocks even when the phase of an input clock is synchronized using a plurality of reference clocks.

According to the present invention for this purpose, the phase detection unit including the RS flip-flop and the D flip-flop is provided with the number of reference clocks. Two neighboring reference clocks among a plurality of reference clocks having the same phase difference are input to the RS flip-flop. The D flip-flop generates an output of the first logic level if the input clock transitions to the first logic level while the output of the RS flip-flop is at the first logic level.

1 is a diagram showing the configuration and operation of a conventional phase-locked loop circuit, (a) is a view showing the concept of the reference clock generation, (b) is a block diagram showing the synchronization signal generator, (c) is a synchronization signal Figure showing the operating characteristics of the generator.

2 is a circuit diagram of a phase locked loop circuit according to the present invention;

3 is a timing diagram showing the operation characteristics of the phase locked loop circuit according to the present invention;

4 is a timing diagram showing an operating characteristic when the phase of the reference clock and the input clock are the same.

Explanation of symbols on the main parts of the drawings

102: multiplexer 104: mixer

202, 204, 206: RS flip-flop 216, 218, 220: D flip-flop

When explaining the preferred embodiment of the present invention made as described above with reference to Figures 2 to 4 as follows.

2 is a circuit diagram of a phase locked loop circuit according to the present invention. As shown in Fig. 2, the RS flip-flop 202 and the D flip-flop 216 form one synchronization signal generation module. Two adjacent reference clocks K0 and K1 are input to the RS flip-flop 202, and the output of the RS flip-flop 202 is input to the D flip-flop 216. The D flip-flop 216 is operated by the input clock CLK_IN to generate the phase detection signal SO. The phase-locked loop circuit according to the present invention includes such a synchronization signal generating module as many as the number of reference clocks K0 to / K3 to detect a section to which the phase of the input clock belongs to each section divided by 360 degrees. . At this time, the detection operation is performed in each module at the same time.

The configuration of the RS flip-flop 202 into which the first reference clock K0 having a zero degree phase and the second reference clock K1 having a 45 degree phase is input will be described below. The first reference clock K0 is inverted by the inverter 208 and input to the first NAND gate 212. The second reference clock K1 is also inverted by another inverter 210 and input to the second NAND gate 214. The output of the first NAND gate 212 is input to the second NAND gate 214, and the output of the second NAND gate 214 is input to the first NAND gate 212. The output of the first NAND gate 212 is input to the D flip-flop 216 as a data signal as the output D1 of the RS flip-flop 202. The D flip-flop 216 is driven by the input clock CLK_IN to activate the first phase detection signal SO, which is an output. At this time, the first phase detection signal S0 is also activated to a high level when the output D1 of the RS flip-flop 202 is at a high level.

3 is a timing diagram showing the operation characteristics of the phase locked loop circuit according to the present invention. Since the two reference clocks Ki (Ki + 1) input to the RS flip-flop have a phase difference of 45 degrees from each other, the output Di of the RS flip-flop has a high level in this 45 degree interval, and a low level in the remaining interval. Has If the input clock CLK_IN is in the region between the reference clock Ki and the second reference clock Ki + 1, the phase detection signal Si, which is the output of the D flip-flop, is also input clock CLK_IN in this 45 degree interval. Will have the same phase as Accordingly, it can be seen that the input clock CLK_IN exists in the region Si between the reference clocks Ki and Ki + 1.

The reference clock Ki (Ki + 1) in the region where the input clock CLK_IN is present is input to the mixer (not shown), and the calculation is performed according to a specific function, thereby synchronizing a signal having the same phase as the input clock ( Kout) will occur. As described above, it can be seen that only one clock is required to detect the phase range of the region where the input clock CLK_IN exists.

If the phase of the input clock CLK_IN is equal to the reference clock Ki or Ki + 1, the phase where the input clock CLK_IN exists because the data setup / hold time of the D flip-flop is not sufficiently secured. It is impossible to detect the range. In FIG. 4, the input clock CLK_IN is shown in phase with the reference clock Ki + 1. To solve this problem, as shown in FIG. 4 (5), the input clock CLK_IN is delayed by the data setup / hold time of the D flip-flop (D _SH ) so that the phase detection signal Si can be activated. After the phase detection signal Si is activated, as shown in Fig. 4 (8), the reference clock is delayed by DSH to restore the state before the input clock CLK_IN is delayed.

To detect when the input clock CLK_IN is in phase with the reference clock Ki, the phase detection signals S0 to S7 are kNOIed, and the delay of the input clock CLK_IN can be determined using the result. have. When the phase of the input clock CLK_IN and the reference clock Ki are the same, no phase detection signal is activated. In this case, the output of the NOR gate is logic 1. This logic 1 signal activates the delay of the input clock CLK_IN.

As such, the present invention provides an effect of significantly shortening the locking time between the input clock and the reference clock by performing phase synchronization during one to two clocks even when the phases of the input clock are synchronized using a plurality of reference clocks.

Claims (3)

In the phase locked loop circuit, An RS flip-flop to which two neighboring reference clocks of a plurality of reference clocks having the same phase difference are input, and an input clock transitions to the first logic level while the output of the RS flip-flop is a first logic level; And a phase detection section composed of D flip-flops for generating an output of a logic level as many as the reference clock. The phase locked loop circuit of claim 1, wherein the input clock is delayed by a data setup / hold time of the D flip-flop when the reference clock input to the synchronization signal generator is in phase. 3. The phase locked loop circuit of claim 2, wherein the input clock is delayed by the data setup / hold time and the reference clock is delayed by the data setup / hold time after a predetermined time has elapsed.