JPH01124729U - - Google Patents
Info
- Publication number
- JPH01124729U JPH01124729U JP2069688U JP2069688U JPH01124729U JP H01124729 U JPH01124729 U JP H01124729U JP 2069688 U JP2069688 U JP 2069688U JP 2069688 U JP2069688 U JP 2069688U JP H01124729 U JPH01124729 U JP H01124729U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- multiplexing
- low
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims 1
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Time-Division Multiplex Systems (AREA)
Description
第１図は本考案によるデイジタル信号中継回路
の基本的構成を示すブロツク図。第２図は従来技
術によるデイジタル信号中継回路の構成を示すブ
ロツク図。第３図は多重数Ｎ＝４の場合の第１図
および第２図の多重回路におけるタイムチヤート
。
１，２１……分離回路、２，２２……Ｄ／Ｉ回
路、３，２３……多重回路、４，２４……計数回
路、５……シフトレジスタ、６……逓倍回路、ａ
……入力デイジタル信号、ｂ……入力デイジタル
信号ａに周期した入力クロツク信号、ｃ……出力
デイジタル信号、ｄ……出力クロツク信号、ｊ，
ｌ……高位クロツク信号、ｅ……抜き出されたデ
イジタル信号、ｆ……挿入するデイジタル信号、
ｇ……多相クロツク信号、ｈ，ｈ′……分離され
た複数の低位デイジタル信号、ｋ……計数回路４
の分周出力クロツク。
FIG. 1 is a block diagram showing the basic configuration of a digital signal relay circuit according to the present invention. FIG. 2 is a block diagram showing the configuration of a digital signal relay circuit according to the prior art. FIG. 3 is a time chart in the multiplex circuit of FIGS. 1 and 2 when the number of multiplexes is N=4. 1, 21... Separation circuit, 2, 22... D/I circuit, 3, 23... Multiplex circuit, 4, 24... Counting circuit, 5... Shift register, 6... Multiplier circuit, a
...Input digital signal, b...Input clock signal with periodicity of input digital signal a, c...Output digital signal, d...Output clock signal, j,
l...high-order clock signal, e...extracted digital signal, f...digital signal to be inserted,
g...multiphase clock signal, h, h'...separated multiple low-order digital signals, k...counting circuit 4
divided output clock.
Claims (1)
に分離する分離回路１と、 多重によつて生成された伝送信号の一部をフレ
ーム同期により抜き出し、あるいは新たに別の信
号を挿入する機能を有する回路２と、 一度分離した低位デイジタル信号を再び多重す
る多重回路３と、 前記分離回路に与えられる低位クロツク信号を
生成する計数回路４と を備えたデイジタル信号中継回路において、 前記多重回路に与えられる低位の多相クロツク
信号を生成するシフトレジスタ５と、 前記計数回路の出力クロツク信号を入力として
多重数倍の周波数をもつ高位クロツク信号を生成
する逓倍回路６と を備えたことを特徴とするデイジタル信号中継
回路。[Claims for Utility Model Registration] A separation circuit 1 that separates an input signal into a plurality of low-level digital signals before multiplexing, and extracts a part of the transmission signal generated by multiplexing by frame synchronization, or converts it into a new and different signal. A digital signal relay circuit comprising a circuit 2 having a function of inserting a signal, a multiplexing circuit 3 for multiplexing once-separated low-order digital signals again, and a counting circuit 4 for generating a low-order clock signal to be applied to the separation circuit. , a shift register 5 that generates a low-order multiphase clock signal to be applied to the multiplex circuit, and a multiplier circuit 6 that receives the output clock signal of the counting circuit as an input and generates a high-order clock signal having a frequency that is multiple times the multiplex number. A digital signal relay circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2069688U JPH01124729U (en) | 1988-02-19 | 1988-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2069688U JPH01124729U (en) | 1988-02-19 | 1988-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01124729U true JPH01124729U (en) | 1989-08-24 |
Family
ID=31237280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2069688U Pending JPH01124729U (en) | 1988-02-19 | 1988-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01124729U (en) |
-
1988
- 1988-02-19 JP JP2069688U patent/JPH01124729U/ja active Pending
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