JPS63149678U - - Google Patents
Info
- Publication number
- JPS63149678U JPS63149678U JP4208287U JP4208287U JPS63149678U JP S63149678 U JPS63149678 U JP S63149678U JP 4208287 U JP4208287 U JP 4208287U JP 4208287 U JP4208287 U JP 4208287U JP S63149678 U JPS63149678 U JP S63149678U
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- clock
- arithmetic circuit
- character multiplex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Television Systems (AREA)
Description
第1図は本考案の一実施例に係る文字多重放送
用符号検出回路の構成図、第2図、第3図は上記
検出回路の具体的構成図、第4図は本考案が適用
される文字多重放送信号の受信装置の構成図、第
5図は従来の受信装置の構成図である。
10……CRI検出信号、60……文字多重信
号、100……文字多重放送用符号検出回路、1
03……シフトレジスタ、105……演算回路。
FIG. 1 is a block diagram of a teletext code detection circuit according to an embodiment of the present invention, FIGS. 2 and 3 are specific block diagrams of the detection circuit, and FIG. 4 is a diagram to which the present invention is applied. A block diagram of a receiving apparatus for teletext broadcasting signals. FIG. 5 is a block diagram of a conventional receiving apparatus. 10... CRI detection signal, 60... Text multiplex signal, 100... Code detection circuit for text multiplex broadcasting, 1
03...Shift register, 105...Arithmetic circuit.
Claims (1)
号が挿入された文字多重信号をサンプリング周波
数mfsのクロツクを用いて2値化して得られる
m逓倍文字多重信号を入力するシフトレジスタと
、このシフトレジスタのm段毎の出力を入力とし
、これと特定パターンとの一致とを検出する演算
回路とを有し、この演算回路の出力より前記クロ
ツクランイン信号の到来を検出することを特徴と
する文字多重放送用符号検出回路。 A shift register receives an m-multiplied character multiplex signal obtained by binarizing a character multiplex signal into which a clock run-in signal with a bit rate frequency fs is inserted using a clock with a sampling frequency mfs, and Code detection for teletext broadcasting, characterized in that it has an arithmetic circuit which takes an output as an input and detects whether the output matches a specific pattern, and detects the arrival of the clock run-in signal from the output of the arithmetic circuit. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4208287U JPS63149678U (en) | 1987-03-24 | 1987-03-24 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4208287U JPS63149678U (en) | 1987-03-24 | 1987-03-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63149678U true JPS63149678U (en) | 1988-10-03 |
Family
ID=30857671
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4208287U Pending JPS63149678U (en) | 1987-03-24 | 1987-03-24 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63149678U (en) |
-
1987
- 1987-03-24 JP JP4208287U patent/JPS63149678U/ja active Pending
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