JPS58101584U - interface circuit - Google Patents

interface circuit

Info

Publication number
JPS58101584U
JPS58101584U JP19402281U JP19402281U JPS58101584U JP S58101584 U JPS58101584 U JP S58101584U JP 19402281 U JP19402281 U JP 19402281U JP 19402281 U JP19402281 U JP 19402281U JP S58101584 U JPS58101584 U JP S58101584U
Authority
JP
Japan
Prior art keywords
pulse
interface circuit
counting
reset
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19402281U
Other languages
Japanese (ja)
Inventor
力 平野
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP19402281U priority Critical patent/JPS58101584U/en
Publication of JPS58101584U publication Critical patent/JPS58101584U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はワイヤレスリモコンによりチャンネル選局を行
なう場合のブロック回路である。第2図は、チャンネル
選局を行なう信号方式である。第3図は本考案の一実施
例に係るリモコン選局信号のインターフェイス回路であ
る。 22.23・・・・・・リセットパルス形成手段、21
゜SW・・・・・・計数パルス取出手段。
FIG. 1 shows a block circuit when channel selection is performed using a wireless remote control. FIG. 2 shows a signal system for channel selection. FIG. 3 shows an interface circuit for a remote control channel selection signal according to an embodiment of the present invention. 22.23...Reset pulse forming means, 21
゜SW・・・Counting pulse extraction means.

Claims (1)

【実用新案登録請求の範囲】 □ 第1の単発パルスと計数パルスとの組合せよりなる
パルスコードと前記第1の単発パルスに対応する第2の
単発パルスとが入力され、前記両単発パルスが同時に存
在することを検出して単発性のリセットパルスを形成す
るリセットパルス形成手段と、 印加される前記リセットパルスに応答して前記パルスコ
ード中の第1の単発パルスと逆極性に前記リセットパル
スを前記パルスコードに加算して前記計数パルスを取出
す計数パルス取出し手段とを備えたことを特徴とするイ
ンターフェイス回路。
[Claims for Utility Model Registration] □ A pulse code consisting of a combination of a first single pulse and a counting pulse and a second single pulse corresponding to the first single pulse are input, and both the single pulses are simultaneously applied. a reset pulse forming means for detecting the presence of the reset pulse and forming a single reset pulse; 1. An interface circuit comprising counting pulse extraction means for adding the counting pulse to a pulse code and extracting the counting pulse.
JP19402281U 1981-12-28 1981-12-28 interface circuit Pending JPS58101584U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19402281U JPS58101584U (en) 1981-12-28 1981-12-28 interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19402281U JPS58101584U (en) 1981-12-28 1981-12-28 interface circuit

Publications (1)

Publication Number Publication Date
JPS58101584U true JPS58101584U (en) 1983-07-11

Family

ID=30107354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19402281U Pending JPS58101584U (en) 1981-12-28 1981-12-28 interface circuit

Country Status (1)

Country Link
JP (1) JPS58101584U (en)

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