JPS62164472U - - Google Patents

Info

Publication number
JPS62164472U
JPS62164472U JP5171486U JP5171486U JPS62164472U JP S62164472 U JPS62164472 U JP S62164472U JP 5171486 U JP5171486 U JP 5171486U JP 5171486 U JP5171486 U JP 5171486U JP S62164472 U JPS62164472 U JP S62164472U
Authority
JP
Japan
Prior art keywords
supplied
output
digital video
video signal
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5171486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5171486U priority Critical patent/JPS62164472U/ja
Publication of JPS62164472U publication Critical patent/JPS62164472U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク線図
、第2図はその説明に供する波形図、第3図及び
第4図は夫々同期信号の説明図である。 2はD/A変換器、3は加算器、4はORゲー
トである。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the same, and FIGS. 3 and 4 are explanatory diagrams of synchronizing signals, respectively. 2 is a D/A converter, 3 is an adder, and 4 is an OR gate.

Claims (1)

【実用新案登録請求の範囲】 シンクチツプの先端が欠如した同期信号を含む
並列n(複数)ビツトのデジタルビデオ信号が供
給されるD/A変換器と、 上記デジタルビデオ信号が供給されるORゲー
トと、 上記D/A変換器の出力及び上記ORゲートの
出力が供給されて加算される加算器とを有し、 該加算器からシンクチツプの先端が復元された
同期信号を含むアナログビデオ信号が出力される
ようにして成るデジタルビデオ信号のD/A変換
回路。
[Claims for Utility Model Registration] A D/A converter to which a parallel n (plural) bit digital video signal including a synchronization signal with a missing tip of a sync chip is supplied; and an OR gate to which the digital video signal is supplied; and an adder to which the output of the D/A converter and the output of the OR gate are supplied and added, and an analog video signal containing a synchronization signal with the tip of the sync chip restored is output from the adder. A D/A conversion circuit for digital video signals.
JP5171486U 1986-04-07 1986-04-07 Pending JPS62164472U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5171486U JPS62164472U (en) 1986-04-07 1986-04-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5171486U JPS62164472U (en) 1986-04-07 1986-04-07

Publications (1)

Publication Number Publication Date
JPS62164472U true JPS62164472U (en) 1987-10-19

Family

ID=30876230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5171486U Pending JPS62164472U (en) 1986-04-07 1986-04-07

Country Status (1)

Country Link
JP (1) JPS62164472U (en)

Similar Documents

Publication Publication Date Title
JPS62164472U (en)
JPH0164229U (en)
JPH01140666U (en)
JPS5882069U (en) Television receiver synchronization separation circuit
JPS6356826U (en)
JPS6219864U (en)
JPS63158066U (en)
JPS62155575U (en)
JPH02143845U (en)
JPS60136548U (en) A/D converter
JPS60145738U (en) Synchronous circuit for asynchronous signals and pulse signals
JPS62110322A (en) Sample-and-hold system
JPS6066132U (en) AD conversion circuit
JPS5927632U (en) A/D converter
JPH0238838U (en)
JPS61146049U (en)
JPS625934U (en)
JPH0197672U (en)
JPH03120185U (en)
JPS6372631U (en)
JPS6413880U (en)
JPS59114663U (en) Vertical synchronization circuit
JPH0398533U (en)
JPS63118647U (en)
JPS63121986U (en)