JPS63121986U - - Google Patents
Info
- Publication number
- JPS63121986U JPS63121986U JP1987012442U JP1244287U JPS63121986U JP S63121986 U JPS63121986 U JP S63121986U JP 1987012442 U JP1987012442 U JP 1987012442U JP 1244287 U JP1244287 U JP 1244287U JP S63121986 U JPS63121986 U JP S63121986U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- synchronization
- supplied
- clock
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の一実施例の受信部を示すブロ
ツク線図、第２図はその送信部を示すブロツク線
図、第３図は同期信号の再生の説明図である。
２は受信処理回路、３はフレームメモリ、４は
Ｄ／Ａ変換器、５は同期付加回路、７はクロツク
／同期発生回路である。
FIG. 1 is a block diagram showing a receiving section of an embodiment of the present invention, FIG. 2 is a block diagram showing its transmitting section, and FIG. 3 is an explanatory diagram of reproduction of a synchronizing signal. 2 is a reception processing circuit, 3 is a frame memory, 4 is a D/A converter, 5 is a synchronization addition circuit, and 7 is a clock/synchronization generation circuit.
Claims (1)
路と、 該受信処理回路からのデジタル映像信号が供給
されるフレームメモリと、 該フレームメモリからのデジタル映像信号が供
給されてアナログ映像信号に変換されるＤ／Ａ変
換器と、 該Ｄ／Ａ変換器からのアナログ映像信号に同期
信号を付加する同期付加回路と、 上記Ｄ／Ａ変換器に供給するクロツク信号を発
生すると共に、該クロツク信号を基にして上記同
期付加回路に供給する垂直同期信号及び水平同期
信号を形成するクロツク／同期発生回路とを有し
、 上記受信処理回路において、上記受信デジタル
映像信号のフイールド信号の区切に応じた垂直同
期信号リセツト信号を得て、上記クロツク／同期
発生回路に供給して、上記垂直同期信号にリセツ
トを掛けるようにして成るテレビジヨン電話装置
。[Claims for Utility Model Registration] A reception processing circuit to which a received digital video signal is supplied; a frame memory to which the digital video signal from the reception processing circuit is supplied; and a frame memory to which the digital video signal is supplied from the frame memory. A D/A converter that converts into an analog video signal, a synchronization addition circuit that adds a synchronization signal to the analog video signal from the D/A converter, and a clock signal that generates a clock signal to be supplied to the D/A converter. and a clock/synchronization generation circuit that forms a vertical synchronization signal and a horizontal synchronization signal to be supplied to the synchronization addition circuit based on the clock signal, and in the reception processing circuit, a field signal of the received digital video signal is provided. 2. A television telephone set which obtains a vertical synchronization signal reset signal according to the division of the vertical synchronization signal and supplies it to the clock/synchronization generation circuit to apply a reset to the vertical synchronization signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987012442U JPH0733500Y2 (en) | 1987-01-30 | 1987-01-30 | Television phone |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987012442U JPH0733500Y2 (en) | 1987-01-30 | 1987-01-30 | Television phone |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63121986U true JPS63121986U (en) | 1988-08-08 |
| JPH0733500Y2 JPH0733500Y2 (en) | 1995-07-31 |
Family
ID=30800574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987012442U Expired - Lifetime JPH0733500Y2 (en) | 1987-01-30 | 1987-01-30 | Television phone |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0733500Y2 (en) |
-
1987
- 1987-01-30 JP JP1987012442U patent/JPH0733500Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0733500Y2 (en) | 1995-07-31 |
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