JPS5755670A - Video display device - Google Patents
Video display deviceInfo
- Publication number
- JPS5755670A JPS5755670A JP55130960A JP13096080A JPS5755670A JP S5755670 A JPS5755670 A JP S5755670A JP 55130960 A JP55130960 A JP 55130960A JP 13096080 A JP13096080 A JP 13096080A JP S5755670 A JPS5755670 A JP S5755670A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- video signal
- synchronizing
- circuit
- scanning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Electric Information Into Light Information (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To improve picture quality substantially by increasing the number of scanning lines of a picture to be displayed and disposing an intermediate video signal, calculated on estimation by video signals on scanning lines before and after each increased scanning line, on the scanning line. CONSTITUTION:A video signal is separated by a synchronous separating circuit 2 and the video signal is encoded by an A/D converter 3 to be stored in a memory 4. Between signals on two scanning lines, a video signal considered to be present on a new scanning line is calculated and inserted to obtain an output composite video signal. This signal is converted into an analog signal by a D/A converter 6. As a synchronizing signal, a composite synchronizing signal is generated by adding a synchronizing signal for interpolating scanning at a synchronizing signal synthesizing circuit 9 in timing as required between input synchronizing signals by a timing circuit 8, and the generated signal is sent from an output terminal 10 to a deflecting circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55130960A JPS5755670A (en) | 1980-09-19 | 1980-09-19 | Video display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55130960A JPS5755670A (en) | 1980-09-19 | 1980-09-19 | Video display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5755670A true JPS5755670A (en) | 1982-04-02 |
Family
ID=15046648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55130960A Pending JPS5755670A (en) | 1980-09-19 | 1980-09-19 | Video display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5755670A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6038992A (en) * | 1983-08-11 | 1985-02-28 | Fujitsu Ltd | Scanning system |
JPS6173483A (en) * | 1984-09-14 | 1986-04-15 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Video signal processor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51110918A (en) * | 1975-03-25 | 1976-09-30 | Mitsubishi Electric Corp |
-
1980
- 1980-09-19 JP JP55130960A patent/JPS5755670A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51110918A (en) * | 1975-03-25 | 1976-09-30 | Mitsubishi Electric Corp |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6038992A (en) * | 1983-08-11 | 1985-02-28 | Fujitsu Ltd | Scanning system |
JPH0218793B2 (en) * | 1983-08-11 | 1990-04-26 | Fujitsu Ltd | |
JPS6173483A (en) * | 1984-09-14 | 1986-04-15 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Video signal processor |
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