JPS5628562A - Clamp circuit - Google Patents

Clamp circuit

Info

Publication number
JPS5628562A
JPS5628562A JP10422479A JP10422479A JPS5628562A JP S5628562 A JPS5628562 A JP S5628562A JP 10422479 A JP10422479 A JP 10422479A JP 10422479 A JP10422479 A JP 10422479A JP S5628562 A JPS5628562 A JP S5628562A
Authority
JP
Japan
Prior art keywords
pulse
clamp
circuit
clamp circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10422479A
Other languages
Japanese (ja)
Inventor
Atsushi Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10422479A priority Critical patent/JPS5628562A/en
Publication of JPS5628562A publication Critical patent/JPS5628562A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/16Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
    • H04N5/185Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit for the black level

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To obtain a clamp circuit where the number of terminal pins can be reduced by one, by making it possible to form a clamp pulse from the flyback pulse. CONSTITUTION:The video signal from input terminal 1 is applied to clamp circuit 2 and is made into video signal S1 with the pedestal level of reference voltage Vr as shown in figure A. Level comparator 9 separates horizontal synchronizing signal Ph shown in figure B from signal S1. Pulse P1 from the flyback transformer shown in figure C is supplied from terminal 8 to shaping circuit 3. Shaped pulse P2 shown in figure D is synthesized with synchronizing pulse Ph by gate 10, and the synthesized pulse is converted to clamp pulse P4 shown in figure E and is applied to clamp circuit 2. Pulse P3 of shaping circuit 3 which is not shown in the figure is applied to a blanking circuit.
JP10422479A 1979-08-16 1979-08-16 Clamp circuit Pending JPS5628562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10422479A JPS5628562A (en) 1979-08-16 1979-08-16 Clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10422479A JPS5628562A (en) 1979-08-16 1979-08-16 Clamp circuit

Publications (1)

Publication Number Publication Date
JPS5628562A true JPS5628562A (en) 1981-03-20

Family

ID=14374983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10422479A Pending JPS5628562A (en) 1979-08-16 1979-08-16 Clamp circuit

Country Status (1)

Country Link
JP (1) JPS5628562A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500688A (en) * 1993-02-26 1996-03-19 Samsung Electronics Co., Ltd. Synchronizing signal clamping circuit of image signal processing integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4925610A (en) * 1972-06-30 1974-03-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4925610A (en) * 1972-06-30 1974-03-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500688A (en) * 1993-02-26 1996-03-19 Samsung Electronics Co., Ltd. Synchronizing signal clamping circuit of image signal processing integrated circuit

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