JPS63163004U - - Google Patents
Info
- Publication number
- JPS63163004U JPS63163004U JP5487187U JP5487187U JPS63163004U JP S63163004 U JPS63163004 U JP S63163004U JP 5487187 U JP5487187 U JP 5487187U JP 5487187 U JP5487187 U JP 5487187U JP S63163004 U JPS63163004 U JP S63163004U
- Authority
- JP
- Japan
- Prior art keywords
- stage
- way
- divider
- output
- output line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
- Details Of Television Systems (AREA)
- Amplifiers (AREA)
Description
第1図はこの考案の一実施例による多分配器を
示す構成図、第2図は従来の多分配器を示す構成
図である。
図において、1は2分配器、2は出力線路の交
差部である。なお図中同一符号は同一又は相当部
分を示す。
FIG. 1 is a block diagram showing a multi-distributor according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional multi-distributor. In the figure, 1 is a two-way divider, and 2 is an intersection of output lines. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
nは2以上の整数)に組み合わせてなり、複数の
出力端子から分配電力を得る多分配器において、 第1ないし第(n―1)段の各2分配器の出力
線路にはそれぞれ2分配器が接続して設けられ、 第1ないし第n段の少なくとも1つの段の2分
配器の出力線路はその少なくとも1つが他の2分
配器の出力線路と交差して設けられ、 第n段の2分配器の出力線路はそれぞれ上記出
力端子に接続して設けられたことを特徴とする多
分配器。[Claims for Utility Model Registration] A two-stage divider that divides the introduced power into two parts (
n is an integer of 2 or more), and in a multi-distributor that obtains distributed power from a plurality of output terminals, the output line of each of the first to (n-1) stage two-way dividers has a two-way divider, respectively. The output lines of at least one of the first to n-th stage two-way dividers are provided so as to intersect with the output line of the other two-way divider, and the n-th stage two-way divider is connected to A multi-distributor characterized in that each output line of the device is connected to the output terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5487187U JPS63163004U (en) | 1987-04-10 | 1987-04-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5487187U JPS63163004U (en) | 1987-04-10 | 1987-04-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63163004U true JPS63163004U (en) | 1988-10-25 |
Family
ID=30882260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5487187U Pending JPS63163004U (en) | 1987-04-10 | 1987-04-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63163004U (en) |
-
1987
- 1987-04-10 JP JP5487187U patent/JPS63163004U/ja active Pending
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