JPH01156636U - - Google Patents
Info
- Publication number
- JPH01156636U JPH01156636U JP5318988U JP5318988U JPH01156636U JP H01156636 U JPH01156636 U JP H01156636U JP 5318988 U JP5318988 U JP 5318988U JP 5318988 U JP5318988 U JP 5318988U JP H01156636 U JPH01156636 U JP H01156636U
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- same number
- output
- circuits
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は従来の一例を示す回路図である。
１…デイジタル回路、２―１〜２―ｎ…バツフ
ア回路、３―１〜３―ｎ…外部端子、４―１〜４
―ｎ…排他的論理和回路、５―１〜５―ｎ…検出
端子、６―１〜６―ｎ…アナログコンパレータ、
７…電源。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing an example of the conventional technology. 1... Digital circuit, 2-1 to 2-n... Buffer circuit, 3-1 to 3-n... External terminal, 4-1 to 4
-n...exclusive OR circuit, 5-1 to 5-n...detection terminal, 6-1 to 6-n...analog comparator,
7...Power supply.
Claims (1)
路と、前記デイジタル回路の各出力端子にそれぞ
れ入力端子を接続した同数のバツフア回路と、前
記各バツフア回路の出力端子を接続した同数の外
部端子と、前記各バツフア回路の出力端子と電源
の出力端子をそれぞれ２つの異なる入力端子に接
続した同数のアナログコンパレータと、前記各バ
ツフア回路の入力端子と前記各アナログコンパレ
ータの出力端子をそれぞれ２つの異なる入力端子
に接続した同数の排他的論理和回路と、前記各排
他的論理和回路の出力端子を接続した同数の検出
端子を含むことを特徴とする出力回路。 a digital circuit having one or more output terminals, the same number of buffer circuits having input terminals connected to each output terminal of the digital circuit, the same number of external terminals having the output terminals of each of the buffer circuits connected; The same number of analog comparators each have the output terminal of each buffer circuit and the output terminal of the power supply connected to two different input terminals, and the input terminal of each buffer circuit and the output terminal of each analog comparator are connected to two different input terminals, respectively. An output circuit comprising the same number of connected exclusive OR circuits and the same number of detection terminals connected to the output terminals of each of the exclusive OR circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5318988U JPH01156636U (en) | 1988-04-19 | 1988-04-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5318988U JPH01156636U (en) | 1988-04-19 | 1988-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01156636U true JPH01156636U (en) | 1989-10-27 |
Family
ID=31279183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5318988U Pending JPH01156636U (en) | 1988-04-19 | 1988-04-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01156636U (en) |
-
1988
- 1988-04-19 JP JP5318988U patent/JPH01156636U/ja active Pending
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