JPH0228133U - - Google Patents
Info
- Publication number
- JPH0228133U JPH0228133U JP10691988U JP10691988U JPH0228133U JP H0228133 U JPH0228133 U JP H0228133U JP 10691988 U JP10691988 U JP 10691988U JP 10691988 U JP10691988 U JP 10691988U JP H0228133 U JPH0228133 U JP H0228133U
- Authority
- JP
- Japan
- Prior art keywords
- input
- voltage
- comparator
- input terminal
- hysteresis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例の回路図、第２図ａ
〜ｅは同実施例の動作を説明するためのタイムチ
ヤート、第３図は本考案の他の実施例の回路図、
第４図は従来のヒステリシスコンパレータの回路
図、第５図ａ及びｂは従来のヒステリシスコンパ
レータの動作を説明するためのタイムチヤートで
ある。
１１……第１のコンパレータ、１２……第２の
コンパレータ、１３……ＥＮＯＲ回路、１４……
遅延回路、１５……フリツプフロツプ、ＶＩＮ…
…入力電圧、ＶＯＵＴ……出力電圧、ＶＨ……第
１の設定電圧、ＶＬ……第２の設定電圧。
Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2a
~e is a time chart for explaining the operation of the same embodiment, FIG. 3 is a circuit diagram of another embodiment of the present invention,
FIG. 4 is a circuit diagram of a conventional hysteresis comparator, and FIGS. 5a and 5b are time charts for explaining the operation of the conventional hysteresis comparator. 11...first comparator, 12...second comparator, 13...ENOR circuit, 14...
Delay circuit, 15...Flip-flop, VIN...
...Input voltage, VOUT...Output voltage, VH...First set voltage, VL...Second set voltage.
Claims (1)
他方の入力端子にヒステリシスの上限電圧となる
第１の設定電圧ＶＨが入力される第１のコンパレ
ータ１１と、 一方の入力端子に入力電圧ＶＩＮが入力され、
他方の入力端子にヒステリシスの下限電圧となる
第２の設定電圧ＶＬが入力される第２のコンパレ
ータ１２と、 該第１、第２のコンパレータのそれぞれの出力
電圧が入力される論理回路１３と、 該論理回路の出力電圧に応じて前記第１もしく
は第２のコンパレータの出力電圧を取り込んで出
力するフリツプフロツプ１５とを備えたことを特
徴とするヒステリシスコンパレータ。[Claims for Utility Model Registration] Input voltage VIN is input to one input terminal,
a first comparator 11 to which a first set voltage VH, which is the upper limit voltage of hysteresis, is input to the other input terminal; and an input voltage VIN to one input terminal;
a second comparator 12 to which the second set voltage VL, which is the lower limit voltage of hysteresis, is input to the other input terminal; a logic circuit 13 to which the output voltages of the first and second comparators are respectively input; A hysteresis comparator comprising a flip-flop 15 which receives and outputs the output voltage of the first or second comparator in accordance with the output voltage of the logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10691988U JPH0228133U (en) | 1988-08-12 | 1988-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10691988U JPH0228133U (en) | 1988-08-12 | 1988-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0228133U true JPH0228133U (en) | 1990-02-23 |
Family
ID=31340861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10691988U Pending JPH0228133U (en) | 1988-08-12 | 1988-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0228133U (en) |
-
1988
- 1988-08-12 JP JP10691988U patent/JPH0228133U/ja active Pending
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