JPS61136634U - - Google Patents
Info
- Publication number
- JPS61136634U JPS61136634U JP1895585U JP1895585U JPS61136634U JP S61136634 U JPS61136634 U JP S61136634U JP 1895585 U JP1895585 U JP 1895585U JP 1895585 U JP1895585 U JP 1895585U JP S61136634 U JPS61136634 U JP S61136634U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- stage
- gate
- monostable multivibrator
- stable level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は、本考案の一実施例を表わす回路図で
あり、第２図は、従来の実施例を表わす回路図で
あり、第３図は、本考案及び従来例の全体構成を
表わす説明図であり、第４図は、第１図の各ノー
ドの電圧を表わす波形図であり、第５図は、第２
図の各ノードの電圧を表わす波形図である。
１１……入力端子、１２……グランド端子、１
３……電源端子、２１……出力端子、３１……Ｎ
ＯＲ回路、３２，３３……インバーター回路、４
１，４２……ダイオード、５１……容量抵抗回路
、５２，５３……実抵抗回路、６１，６２，６３
，６４，６５，６６，６７，６８……ノード、７
１……負荷抵抗（メロデイーＩＣ）、７２……負
荷抵抗（スピーカー）、７３……電源、７４……
スイツチ、Ｌ……低電圧値、Ｈ……高電圧値、Ｔ
……しきい値。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional embodiment, and FIG. 3 is an explanation showing the overall configuration of the present invention and the conventional example. 4 is a waveform diagram showing the voltage at each node in FIG. 1, and FIG. 5 is a waveform diagram showing the voltage at each node in FIG.
FIG. 3 is a waveform diagram showing voltages at each node in the figure. 11...Input terminal, 12...Ground terminal, 1
3...Power terminal, 21...Output terminal, 31...N
OR circuit, 32, 33... Inverter circuit, 4
1, 42... Diode, 51... Capacitance resistance circuit, 52, 53... Actual resistance circuit, 61, 62, 63
, 64, 65, 66, 67, 68... node, 7
1...Load resistance (Melody IC), 72...Load resistance (speaker), 73...Power supply, 74...
Switch, L...Low voltage value, H...High voltage value, T
……threshold.
Claims (1)
び前記後段の間の微分回路よりなる、準安定レベ
ルのパルスを前記前後のゲートの入力に加えると
、前記後段のゲートの出力が準安定レベルとなり
、一定の時間を経過すると自動的に前記後段のゲ
ートの出力レベルが安定レベルとなる単安定マイ
チバイブレーター回路に於いて、前記後段のゲー
トの出力が安定レベルのときのみ前記後段のゲー
トの入力へ安定化帰還電流が流れるよう働く帰還
回路が前記後段のゲートに設けられた事を特徴と
する単安定マルチバイブレーター回路。 (2) 前段のゲートがＮＯＲ回路よりなり、微分
回路が容量抵抗回路と実抵抗回路よりなり、後段
のゲートがインバーター回路よりなる実用新案登
録請求の範囲第１項記載の単安定マルチバイブレ
ーター回路。 (3) 帰還回路がインバーター回路とダイオード
よりなる実用新案登録請求の範囲第１項及び第２
項記載の単安定マルチバイブレーター回路。[Claims for Utility Model Registration] (1) When a pulse at a quasi-stable level is applied to the inputs of the front and rear gates, which are composed of a front-stage gate, a rear-stage gate, and a differential circuit between the front-stage and the rear-stage gates, the rear-stage In a monostable michi vibrator circuit, the output of the gate in the second stage becomes a quasi-stable level, and the output level of the gate in the second stage automatically becomes a stable level after a certain period of time has passed. 1. A monostable multivibrator circuit, characterized in that a feedback circuit is provided in the gate of the latter stage, which operates so that a stabilizing feedback current flows to the input of the gate of the latter stage only when the monostable multivibrator circuit is in use. (2) The monostable multivibrator circuit according to claim 1, wherein the first stage gate is composed of a NOR circuit, the differentiating circuit is composed of a capacitive resistance circuit and a real resistance circuit, and the second stage gate is composed of an inverter circuit. (3) Claims 1 and 2 for utility model registration in which the feedback circuit consists of an inverter circuit and a diode
Monostable multivibrator circuit as described in Section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985018955U JPH0546350Y2 (en) | 1985-02-13 | 1985-02-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985018955U JPH0546350Y2 (en) | 1985-02-13 | 1985-02-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61136634U true JPS61136634U (en) | 1986-08-25 |
| JPH0546350Y2 JPH0546350Y2 (en) | 1993-12-03 |
Family
ID=30508076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985018955U Expired - Lifetime JPH0546350Y2 (en) | 1985-02-13 | 1985-02-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0546350Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5233454A (en) * | 1975-09-10 | 1977-03-14 | Mitsubishi Electric Corp | Mono stabel multi vibrator |
| JPS5686528A (en) * | 1979-12-18 | 1981-07-14 | Nec Corp | Pulse circuit |
-
1985
- 1985-02-13 JP JP1985018955U patent/JPH0546350Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5233454A (en) * | 1975-09-10 | 1977-03-14 | Mitsubishi Electric Corp | Mono stabel multi vibrator |
| JPS5686528A (en) * | 1979-12-18 | 1981-07-14 | Nec Corp | Pulse circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0546350Y2 (en) | 1993-12-03 |
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