JPH0338933U - - Google Patents
Info
- Publication number
- JPH0338933U JPH0338933U JP9824189U JP9824189U JPH0338933U JP H0338933 U JPH0338933 U JP H0338933U JP 9824189 U JP9824189 U JP 9824189U JP 9824189 U JP9824189 U JP 9824189U JP H0338933 U JPH0338933 U JP H0338933U
- Authority
- JP
- Japan
- Prior art keywords
- drain
- resistor
- time constant
- gaas
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
Description
第1図は本考案に係る差動増幅器の一実施例を
示す構成図、第2図および第3図は出力波形を示
す図、第4図は等価回路、第5図は従来の高速波
形出力回路の最終段の一例を示す図、第6図ない
し第8図はGaAs−FETの特性を説明するた
めの図、第9図は従来の回路の入出力波形を示す
図である。
Q1,Q2……GaAs−FET、CS……定
電流源、11,12,21,22……伝送線路、
R1,R2,R3,R11,R12,R13……
抵抗、C1,C11……コンデンサ。
Figure 1 is a block diagram showing an embodiment of the differential amplifier according to the present invention, Figures 2 and 3 are diagrams showing output waveforms, Figure 4 is an equivalent circuit, and Figure 5 is a conventional high-speed waveform output. A diagram showing an example of the final stage of the circuit, FIGS. 6 to 8 are diagrams for explaining characteristics of a GaAs-FET, and FIG. 9 is a diagram showing input and output waveforms of a conventional circuit. Q1 , Q2 ...GaAs-FET, CS...constant current source, 11, 12, 21, 22...transmission line,
R 1 , R 2 , R 3 , R 11 , R 12 , R 13 ...
Resistor, C 1 , C 11 ... capacitor.
Claims (1)
されると共に、各ドレインには抵抗を介してそれ
ぞれ電源電圧が印加され、かつゲートには相補的
入力が与えられる2つのGaAs−FETと、 CR並列接続回路と伝送線路の直列回路を介し
て前記FETのドレインに接続される終端抵抗よ
りなり、前記CR並列接続回路の時定数を、前記
GaAs−FETのドレインに前記抵抗のみ接続
した場合のドレイン電圧の立ち上がり後のなだら
かな変化の時定数と等しくなるように設定し、相
補的入力に対応して終端抵抗より高速応答の出力
が得られるようにしたことを特徴とする差動増幅
回路。[Claims for Utility Model Registration] Their sources are commonly connected and connected to a constant current source, a power supply voltage is applied to each drain via a resistor, and complementary inputs are given to the gates. It consists of two GaAs-FETs and a terminating resistor connected to the drain of the FET through a series circuit of a CR parallel connection circuit and a transmission line, and the time constant of the CR parallel connection circuit is set to the drain of the GaAs-FET. The time constant is set to be equal to the time constant of the gradual change after the rise of the drain voltage when only the resistor is connected, so that an output with a faster response than the terminating resistor can be obtained in response to complementary inputs. A differential amplifier circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9824189U JPH0713302Y2 (en) | 1989-08-23 | 1989-08-23 | Differential amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9824189U JPH0713302Y2 (en) | 1989-08-23 | 1989-08-23 | Differential amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0338933U true JPH0338933U (en) | 1991-04-15 |
JPH0713302Y2 JPH0713302Y2 (en) | 1995-03-29 |
Family
ID=31647350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9824189U Expired - Lifetime JPH0713302Y2 (en) | 1989-08-23 | 1989-08-23 | Differential amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0713302Y2 (en) |
-
1989
- 1989-08-23 JP JP9824189U patent/JPH0713302Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0713302Y2 (en) | 1995-03-29 |