JPS61195123U - - Google Patents
Info
- Publication number
- JPS61195123U JPS61195123U JP7365685U JP7365685U JPS61195123U JP S61195123 U JPS61195123 U JP S61195123U JP 7365685 U JP7365685 U JP 7365685U JP 7365685 U JP7365685 U JP 7365685U JP S61195123 U JPS61195123 U JP S61195123U
- Authority
- JP
- Japan
- Prior art keywords
- comparators
- series
- input
- output
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
ａ，ｂ，ｃ，ｄは第１図に示された実施例の動作
を示す波形図である。
１，２，１２，１３……ＭＯＳＦＥＴ、３，４
，５……抵抗、６，７……コンパレータ、８，９
……ＮＯＲゲート、１０……Ｒ―Ｓフリツプフロ
ツプ、１１……インバータ、１４……コンデンサ
、１５……バツフア。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2a, b, c, and d are waveform diagrams showing the operation of the embodiment shown in FIG. 1, 2, 12, 13...MOSFET, 3, 4
, 5... Resistor, 6, 7... Comparator, 8, 9
...NOR gate, 10...RS flip-flop, 11...inverter, 14...capacitor, 15...buffer.
Claims (1)
Ｔによつて発生される基準電圧が一方の入力端に
印加された２個のコンパレータと、該２個のコン
パレータの他方の入力端に各々分割された電圧を
印加するための電源電圧間に直列接続された分割
抵抗と、前記２個のコンパレータの一方の出力及
び他方の反転出力を入出とするＲ―Ｓフリツプフ
ロツプと、該Ｒ―Ｓフリツプフロツプの出力がゲ
ートに印加されたエンハンスメント型のＭＯＳＦ
ＥＴと、該ＭＯＳＦＥＴと共に電源電圧間に直列
接続されたデプレツシヨン型のＭＯＳＦＥＴと、
前記エンハンスメント型のＭＯＳＦＥＴに並列接
続されたコンデンサと、該コンデンサの端子電圧
を入力とするバツフアあるいはインバータとから
成るリセツト回路。 Multiple MOSFEs connected in series between supply voltages
The reference voltage generated by T is connected in series between two comparators to which the reference voltage is applied to one input, and the power supply voltage for applying the divided voltage to the other input of the two comparators. A connected dividing resistor, an RS flip-flop whose inputs and outputs are one output and the inverted output of the other of the two comparators, and an enhancement type MOSF to which the output of the RS flip-flop is applied to the gate.
ET, a depletion type MOSFET connected in series with the MOSFET between the power supply voltages,
A reset circuit comprising a capacitor connected in parallel to the enhancement type MOSFET, and a buffer or inverter that receives the terminal voltage of the capacitor as input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7365685U JPS61195123U (en) | 1985-05-17 | 1985-05-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7365685U JPS61195123U (en) | 1985-05-17 | 1985-05-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61195123U true JPS61195123U (en) | 1986-12-05 |
Family
ID=30613223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7365685U Pending JPS61195123U (en) | 1985-05-17 | 1985-05-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61195123U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01171318A (en) * | 1987-12-01 | 1989-07-06 | Sgs Thomson Microelettronica Spa | Closing reset circuit device of digital integrated circuit in mos technology |
-
1985
- 1985-05-17 JP JP7365685U patent/JPS61195123U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01171318A (en) * | 1987-12-01 | 1989-07-06 | Sgs Thomson Microelettronica Spa | Closing reset circuit device of digital integrated circuit in mos technology |
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