JPS5927631U - Waveform shaping device - Google Patents

Waveform shaping device

Info

Publication number
JPS5927631U
JPS5927631U JP12224182U JP12224182U JPS5927631U JP S5927631 U JPS5927631 U JP S5927631U JP 12224182 U JP12224182 U JP 12224182U JP 12224182 U JP12224182 U JP 12224182U JP S5927631 U JPS5927631 U JP S5927631U
Authority
JP
Japan
Prior art keywords
distribution circuit
operational amplifier
shaping device
waveform shaping
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12224182U
Other languages
Japanese (ja)
Inventor
実 高瀬
Original Assignee
日本サ−ボ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本サ−ボ株式会社 filed Critical 日本サ−ボ株式会社
Priority to JP12224182U priority Critical patent/JPS5927631U/en
Publication of JPS5927631U publication Critical patent/JPS5927631U/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは従来の波形整形装置の回路図、第1図b−d
は夫々その各部の信号波形図、第1図eはそのオペアン
プの回路図、第1図fはそのNANDゲートに対する入
力信号波形図、第1図g′はNANDゲートに対する入
力電圧の許容値説明図、第2図aは従来の他の波形整形
装置の回路図、第2図すはそのNANDゲートに対する
入力信号波形図、第3図aは本考案装置の回路図、第3
図すはそのNANDゲートに対する入力信号波形図であ
る。 1・・・交流信号の発生源、2・・・オペアンプ、3゜
4・・・NANI)’r’−ト、5・・・コンパレータ
、6.7・・・基準電圧分配器、8.11・・・抵抗、
10・・・ダイオード。
Figure 1a is a circuit diagram of a conventional waveform shaping device, Figures 1b-d
are signal waveform diagrams of each part, Figure 1e is a circuit diagram of the operational amplifier, Figure 1f is an input signal waveform diagram for the NAND gate, and Figure 1g' is a diagram explaining the allowable value of input voltage for the NAND gate. , FIG. 2a is a circuit diagram of another conventional waveform shaping device, FIG. 2 is an input signal waveform diagram for the NAND gate, FIG. 3a is a circuit diagram of the device of the present invention,
The figure is an input signal waveform diagram for the NAND gate. DESCRIPTION OF SYMBOLS 1... Source of AC signal, 2... Operational amplifier, 3°4... NANI)'r'-to, 5... Comparator, 6.7... Reference voltage divider, 8.11 ···resistance,
10...Diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流信号をこれと同一周期のパルス信号に変換するオペ
アンプと、このオペアンプからのパルス信号を定められ
た順序で複数の回路に分配する分配回路と、上記オペア
ンプの出力側と分配回路の□入力側に介挿した逆方向ダ
イオードと、上記パルス分配回路の入力側と電源間に介
挿した抵抗とより成ることを特徴とする波形整形装置。
An operational amplifier that converts an alternating current signal into a pulse signal with the same period as this, a distribution circuit that distributes the pulse signal from this operational amplifier to multiple circuits in a predetermined order, and the output side of the operational amplifier and the input side of the distribution circuit. A waveform shaping device comprising: a reverse diode inserted into the pulse distribution circuit; and a resistor inserted between the input side of the pulse distribution circuit and a power supply.
JP12224182U 1982-08-13 1982-08-13 Waveform shaping device Pending JPS5927631U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12224182U JPS5927631U (en) 1982-08-13 1982-08-13 Waveform shaping device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12224182U JPS5927631U (en) 1982-08-13 1982-08-13 Waveform shaping device

Publications (1)

Publication Number Publication Date
JPS5927631U true JPS5927631U (en) 1984-02-21

Family

ID=30279488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12224182U Pending JPS5927631U (en) 1982-08-13 1982-08-13 Waveform shaping device

Country Status (1)

Country Link
JP (1) JPS5927631U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005518746A (en) * 2002-02-26 2005-06-23 ザ リージェンツ オブ ザ ユニバーシティ オブ ミシガン MEM-based computer system and clock generation oscillator circuit and LC tank device used therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5458323A (en) * 1977-10-19 1979-05-11 Fujitsu Ltd Interface circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5458323A (en) * 1977-10-19 1979-05-11 Fujitsu Ltd Interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005518746A (en) * 2002-02-26 2005-06-23 ザ リージェンツ オブ ザ ユニバーシティ オブ ミシガン MEM-based computer system and clock generation oscillator circuit and LC tank device used therefor

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