JPS59137643U - A-D converter - Google Patents
A-D converterInfo
- Publication number
- JPS59137643U JPS59137643U JP3106683U JP3106683U JPS59137643U JP S59137643 U JPS59137643 U JP S59137643U JP 3106683 U JP3106683 U JP 3106683U JP 3106683 U JP3106683 U JP 3106683U JP S59137643 U JPS59137643 U JP S59137643U
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- outputs
- converter
- voltage
- voltage comparators
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
□ 第１図はこの考案の説明に供する従来のＡ−Ｄコン
バータの接続図、第２図及び第３゛図は夫々この考案に
係わるＡ−Ｄコンバータの一例を示す接５７７′７札Ｂ
−、１□、、、、工□１６，５゜。
５Ｂ・・・・・・はアンド回路、Ｄ〜、 Ｄｂ、・・曲
はダイオード、Ｒ＋Ｊｉ負荷抵抗器、３はエンコーダー
である。□ Fig. 1 is a connection diagram of a conventional A-D converter to explain this invention, and Figs. 2 and 3 are connection diagrams showing an example of an A-D converter according to this invention.
-, 1□,,,, 16.5°. 5B... is an AND circuit, D~, Db,... is a diode, R+Ji is a load resistor, and 3 is an encoder.
Claims (1)
のうち互いに隣り合う電圧比較器より得・ られる出
力同士をアンドする複数のアンド回路と、これら複数の
アンド出力をエンコードして上記入力電圧に対応したコ
ード出力を得るエンコーダーとを有し、上記アンド回路
は夫々ダイオードアンドで構成されて成るＡ−Ｄコンバ
ータ。A plurality of voltage comparators that compare input voltages, a plurality of AND circuits that AND the outputs obtained from adjacent voltage comparators among their respective outputs, and a plurality of AND circuits that encode the plurality of AND outputs to output the above inputs. and an encoder for obtaining a code output corresponding to the voltage, and each of the AND circuits is constituted by a diode AND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3106683U JPS59137643U (en) | 1983-03-03 | 1983-03-03 | A-D converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3106683U JPS59137643U (en) | 1983-03-03 | 1983-03-03 | A-D converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59137643U true JPS59137643U (en) | 1984-09-13 |
Family
ID=30161920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3106683U Pending JPS59137643U (en) | 1983-03-03 | 1983-03-03 | A-D converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59137643U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51139245A (en) * | 1975-04-02 | 1976-12-01 | Nadler Morton | Method of converting analog to digital and converter therefor |
-
1983
- 1983-03-03 JP JP3106683U patent/JPS59137643U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51139245A (en) * | 1975-04-02 | 1976-12-01 | Nadler Morton | Method of converting analog to digital and converter therefor |
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